Revert "flashchips: port S25FS(128S) chip from chromiumos"

This reverts commit a3519561bd0fb44153bb376322b799000657576f.

Breaks support for most SPI flash chips. It's too big and too
invasive to be reviewed as a single commit.

The changes to `spi_poll_wip():spi25.c` were not noticed in the
original review that were from the similarly named function and
file `s25f_poll_status():s25f.c` in the downstream Chromium fork.

V.2: Rebase and rephrase commit msg to reflect how the issue
     slipped in.

Change-Id: Id2a4593bdb654f8a26957d69d52189ce61621d93
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shiyu Sun <sshiyu@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

1 files changed, 4 insertions, 214 deletions

diff --git a/spi25.c b/spi25.c
index 16d7f1b1d..0a939e7db 100644
--- a/spi25.c
+++ b/spi25.c
@@ -25,7 +25,6 @@
 #include "flashchips.h"
 #include "chipdrivers.h"
 #include "programmer.h"
-#include "hwaccess.h"
 #include "spi.h"
 
 static int spi_rdid(struct flashctx *flash, unsigned char *readarr, int bytes)
@@ -285,155 +284,13 @@ int probe_spi_at25f(struct flashctx *flash)
 	return 0;
 }
 
-/* Used for probing 'big' Spansion/Cypress S25FS chips */
-int probe_spi_big_spansion(struct flashctx *flash)
+static int spi_poll_wip(struct flashctx *const flash, const unsigned int poll_delay)
 {
-	static const unsigned char cmd = JEDEC_RDID;
-	int ret;
-	unsigned char dev_id[6]; /* We care only about 6 first bytes */
-
-	ret = spi_send_command(flash, sizeof(cmd), sizeof(dev_id), &cmd, dev_id);
-
-	if (!ret) {
-		unsigned long i;
-
-		for (i = 0; i < sizeof(dev_id); i++)
-			msg_gdbg(" 0x%02x", dev_id[i]);
-		msg_gdbg(".\n");
-
-		if (dev_id[0] == flash->chip->manufacture_id) {
-			union {
-				uint8_t array[4];
-				uint32_t whole;
-			} model_id;
-
-	/*
-	 * The structure of the RDID output is as follows:
-	 *
-	 *     offset   value              meaning
-	 *       00h     01h      Manufacturer ID for Spansion
-	 *       01h     20h           128 Mb capacity
-	 *       01h     02h           256 Mb capacity
-	 *       02h     18h           128 Mb capacity
-	 *       02h     19h           256 Mb capacity
-	 *       03h     4Dh       Full size of the RDID output (ignored)
-	 *       04h     00h       FS: 256-kB physical sectors
-	 *       04h     01h       FS: 64-kB physical sectors
-	 *       04h     00h       FL: 256-kB physical sectors
-	 *       04h     01h       FL: Mix of 64-kB and 4KB overlayed sectors
-	 *       05h     80h       FL family
-	 *       05h     81h       FS family
-	 *
-	 * Need to use bytes 1, 2, 4, and 5 to properly identify one of eight
-	 * possible chips:
-	 *
-	 * 2 types * 2 possible sizes * 2 possible sector layouts
-	 *
-	 */
-			memcpy(model_id.array, dev_id + 1, 2);
-			memcpy(model_id.array + 2, dev_id + 4, 2);
-			if (be_to_cpu32(model_id.whole) == flash->chip->model_id)
-				return 1;
-		}
-	}
-
-	return 0;
-}
-
-/* Used for Spansion/Cypress S25F chips */
-static int s25f_legacy_software_reset(struct flashctx *flash)
-{
-	int result;
-	struct spi_command cmds[] = {
-	{
-		.writecnt	= 1,
-		.writearr	= (const unsigned char[]){ CMD_RSTEN },
-		.readcnt	= 0,
-		.readarr	= NULL,
-	}, {
-		.writecnt	= 1,
-		.writearr	= (const unsigned char[]){ 0xf0 },
-		.readcnt	= 0,
-		.readarr	= NULL,
-	}, {
-		.writecnt	= 0,
-		.writearr	= NULL,
-		.readcnt	= 0,
-		.readarr	= NULL,
-	}};
-
-	result = spi_send_multicommand(flash, cmds);
-	if (result) {
-		msg_cerr("%s failed during command execution\n", __func__);
-		return result;
-	}
-	/* Reset takes 35us according to data-sheet, double that for safety */
-	programmer_delay(T_RPH * 2);
-
-	return 0;
-}
-
-/* Only for Spansion S25FS chips, where legacy reset is disabled by default */
-int s25fs_software_reset(struct flashctx *flash)
-{
-	int result;
-	struct spi_command cmds[] = {
-	{
-		.writecnt	= 1,
-		.writearr	= (const unsigned char[]){ CMD_RSTEN },
-		.readcnt	= 0,
-		.readarr	= NULL,
-	}, {
-		.writecnt	= 1,
-		.writearr	= (const unsigned char[]){ CMD_RST },
-		.readcnt	= 0,
-		.readarr	= NULL,
-	}, {
-		.writecnt	= 0,
-		.writearr	= NULL,
-		.readcnt	= 0,
-		.readarr	= NULL,
-	}};
-
-	msg_cdbg("Force resetting SPI chip.\n");
-	result = spi_send_multicommand(flash, cmds);
-	if (result) {
-		msg_cerr("%s failed during command execution\n", __func__);
-		return result;
-	}
-
-	programmer_delay(T_RPH * 2);
-
-	return 0;
-}
-
-int spi_poll_wip(struct flashctx *const flash, const unsigned int poll_delay)
-{
-	uint8_t status_reg = spi_read_status_register(flash);
-
+	/* FIXME: We can't tell if spi_read_status_register() failed. */
 	/* FIXME: We don't time out. */
-	while (status_reg & SPI_SR_WIP) {
-		/*
-		 * The WIP bit on S25F chips remains set to 1 if erase or
-		 * programming errors occur, so we must check for those
-		 * errors here. If an error is encountered, do a software
-		 * reset to clear WIP and other volatile bits, otherwise
-		 * the chip will be unresponsive to further commands.
-		 */
-		if (status_reg & SPI_SR_ERA_ERR) {
-			msg_cerr("Erase error occurred\n");
-			s25f_legacy_software_reset(flash);
-			return -1;
-		}
-		if (status_reg & (1 << 6)) {
-			msg_cerr("Programming error occurred\n");
-			s25f_legacy_software_reset(flash);
-			return -1;
-		}
+	while (spi_read_status_register(flash) & SPI_SR_WIP)
 		programmer_delay(poll_delay);
-		status_reg = spi_read_status_register(flash);
-	}
-
+	/* FIXME: Check the status register for errors. */
 	return 0;
 }
 
@@ -631,73 +488,6 @@ int spi_block_erase_d8(struct flashctx *flash, unsigned int addr,
 	return spi_write_cmd(flash, 0xd8, false, addr, NULL, 0, 100 * 1000);
 }
 
-/* Used on Spansion/Cypress S25FS chips */
-int s25fs_block_erase_d8(struct flashctx *flash,
-		unsigned int addr, unsigned int blocklen)
-{
-	unsigned char cfg;
-	int result;
-	static int cr3nv_checked = 0;
-
-	struct spi_command erase_cmds[] = {
-	{
-		.writecnt	= JEDEC_WREN_OUTSIZE,
-		.writearr	= (const unsigned char[]){ JEDEC_WREN },
-		.readcnt	= 0,
-		.readarr	= NULL,
-	}, {
-		.writecnt	= JEDEC_BE_D8_OUTSIZE,
-		.writearr	= (const unsigned char[]){
-					JEDEC_BE_D8,
-					(addr >> 16) & 0xff,
-					(addr >> 8) & 0xff,
-					(addr & 0xff)
-				},
-		.readcnt	= 0,
-		.readarr	= NULL,
-	}, {
-		.writecnt	= 0,
-		.writearr	= NULL,
-		.readcnt	= 0,
-		.readarr	= NULL,
-	}};
-
-	/* Check if hybrid sector architecture is in use and, if so,
-	 * switch to uniform sectors. */
-	if (!cr3nv_checked) {
-		cfg = s25fs_read_cr(flash, CR3NV_ADDR);
-		if (!(cfg & CR3NV_20H_NV)) {
-			s25fs_write_cr(flash, CR3NV_ADDR, cfg | CR3NV_20H_NV);
-			s25fs_software_reset(flash);
-
-			cfg = s25fs_read_cr(flash, CR3NV_ADDR);
-			if (!(cfg & CR3NV_20H_NV)) {
-				msg_cerr("%s: Unable to enable uniform "
-					"block sizes.\n", __func__);
-				return 1;
-			}
-
-			msg_cdbg("\n%s: CR3NV updated (0x%02x -> 0x%02x)\n",
-					__func__, cfg,
-					s25fs_read_cr(flash, CR3NV_ADDR));
-			/* Restore CR3V when flashrom exits */
-			register_chip_restore(s25fs_restore_cr3nv, flash, cfg);
-		}
-
-		cr3nv_checked = 1;
-	}
-
-	result = spi_send_multicommand(flash, erase_cmds);
-	if (result) {
-		msg_cerr("%s failed during command execution at address 0x%x\n",
-			__func__, addr);
-		return result;
-	}
-
-	programmer_delay(T_SE);
-	return spi_poll_wip(flash, 1000 * 10);
-}
-
 /* Block size is usually
  * 4k for PMC
  */