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| author | Wei Hu <wei@aristanetworks.com> | 2018-04-30 14:02:08 -0700 |
|---|---|---|
| committer | David Hendricks <david.hendricks@gmail.com> | 2018-05-06 20:56:02 +0000 |
| commit | 25584de9d0108a5dde41e0296fdf0a7854390a81 (patch) | |
| tree | d505c037e5a2e729e1eb64882c60fd69fcb1b40e /spi25_statusreg.c | |
| parent | 1b365931ea8a9d5766972c17c7cf91b9de595fb1 (diff) | |
| download | flashrom-25584de9d0108a5dde41e0296fdf0a7854390a81.tar.gz flashrom-25584de9d0108a5dde41e0296fdf0a7854390a81.tar.bz2 flashrom-25584de9d0108a5dde41e0296fdf0a7854390a81.zip | |
flashchips: Add SST26VF016B(A), SST26VF032B(A), SST26VF064B(A)
This patch seems to have originally been from
https://patchwork.coreboot.org/patch/4126/ . The most recent version
seems to be in OpenEmbedded (commit 503a572) which added support for
16Mbit and 32Mbit variants.
The OpenEmbedded patch also makes changes to linux_spi.c to add some
debug prints which are omitted in this version.
From the original commit message:
Differences between SST26 and SST25:
1. The WREN instruction must be executed prior to WRSR [Section 5.31].
There is no EWSR.
2. Block protection bits are no longer in the status register. There
is a dedicated 144-bit register [Table 5-6]. The device is
write-protected by default. A Global Block-Protection Unlock
command unlocks the entire memory [Section 4.1].
Change-Id: Ib019bed8ce955049703eb3376c32a83ef607c219
Signed-off-by: Wei Hu <wei@aristanetworks.com>
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
Reviewed-on: https://review.coreboot.org/25962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'spi25_statusreg.c')
| -rw-r--r-- | spi25_statusreg.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/spi25_statusreg.c b/spi25_statusreg.c index 67d676c79..a5fb3b8bd 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -195,6 +195,19 @@ int spi_disable_blockprotect(struct flashctx *flash) return spi_disable_blockprotect_generic(flash, 0x3C, 0, 0, 0xFF); } +int spi_disable_blockprotect_sst26_global_unprotect(struct flashctx *flash) +{ + int result = spi_write_enable(flash); + if (result) + return result; + + static const unsigned char cmd[] = { 0x98 }; /* ULBPR */ + result = spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); + if (result) + msg_cerr("ULBPR failed\n"); + return result; +} + /* A common block protection disable that tries to unset the status register bits masked by 0x0C (BP0-1) and * protected/locked by bit #7. Useful when bits 4-5 may be non-0). */ int spi_disable_blockprotect_bp1_srwd(struct flashctx *flash) |