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| author | Nikolai Artemiev <nartemiev@google.com> | 2022-11-02 11:30:57 +1100 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2022-12-06 03:12:55 +0000 |
| commit | 49bcb78006d88189bb13513982f3fa734b441641 (patch) | |
| tree | 11586cf450e59b78d94a530b74028b04888da288 /spi25_statusreg.c | |
| parent | 62ec7b7156e1b35da66f54f6d493b38a9e78f94c (diff) | |
| download | flashrom-49bcb78006d88189bb13513982f3fa734b441641.tar.gz flashrom-49bcb78006d88189bb13513982f3fa734b441641.tar.bz2 flashrom-49bcb78006d88189bb13513982f3fa734b441641.zip | |
writeprotect,ichspi,spi25: handle register access constraints
Make the spi25 register read/write functions return SPI_INVALID_OPCODE
if the programmer blocks the read/write opcode for the register.
Likewise, make ichspi read/write register functions return
SPI_INVALID_OPCODE for registers >SR1 as they cannot be accessd.
Make writeprotect ignore SPI_INVALID_OPCODE unless it is trying to
read/write SR1, which should always be supported.
BUG=b:253715389,b:253713774,b:240229722
BRANCH=none
TEST=flashrom --wp-{enable,disable,range,list,status} on dedede
Change-Id: I2145749dcc51f4556550650dab5aa1049f879c45
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/69129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Diffstat (limited to 'spi25_statusreg.c')
| -rw-r--r-- | spi25_statusreg.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/spi25_statusreg.c b/spi25_statusreg.c index b178b2e37..726ca8cc9 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -19,6 +19,7 @@ #include "flash.h" #include "chipdrivers.h" +#include "programmer.h" #include "spi.h" /* === Generic functions === */ @@ -129,6 +130,11 @@ int spi_write_register(const struct flashctx *flash, enum flash_reg reg, uint8_t return 1; } + if (!flash->mst->spi.probe_opcode(flash, write_cmd[0])) { + msg_pdbg("%s: write to register %d not supported by programmer, ignoring.\n", __func__, reg); + return SPI_INVALID_OPCODE; + } + uint8_t enable_cmd; if (feature_bits & FEATURE_WRSR_WREN) { enable_cmd = JEDEC_WREN; @@ -238,6 +244,11 @@ int spi_read_register(const struct flashctx *flash, enum flash_reg reg, uint8_t return 1; } + if (!flash->mst->spi.probe_opcode(flash, read_cmd)) { + msg_pdbg("%s: read from register %d not supported by programmer.\n", __func__, reg); + return SPI_INVALID_OPCODE; + } + /* FIXME: No workarounds for driver/hardware bugs in generic code. */ /* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */ uint8_t readarr[2]; |