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authorNico Huber <nico.h@gmx.de>2022-08-14 11:50:41 +0200
committerThomas Heijligen <src@posteo.de>2022-08-17 19:41:46 +0000
commitcd4a62a7841ab794b654554778399fbc76933344 (patch)
treee84a74dfa1e3f9df3b2c7cca391ed38f7fe67b71 /spi25_statusreg.c
parent99eca0899b931b21b7c44ed1753c5f01b35798af (diff)
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spi25_statusreg: Fix checks for FEATURE_WRSR_EXT3
FEATURE_WRSR_EXT3 contains multiple bits, hence we need to check for all of them. Change-Id: I188911890361999cd8cca9b6405f57a91075f6b4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reported-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-by: Thomas Heijligen <src@posteo.de>
Diffstat (limited to 'spi25_statusreg.c')
-rw-r--r--spi25_statusreg.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/spi25_statusreg.c b/spi25_statusreg.c
index 4cd19aba0..5dbba75ca 100644
--- a/spi25_statusreg.c
+++ b/spi25_statusreg.c
@@ -93,7 +93,7 @@ int spi_write_register(const struct flashctx *flash, enum flash_reg reg, uint8_t
write_cmd_len = JEDEC_WRSR3_OUTSIZE;
break;
}
- if (feature_bits & FEATURE_WRSR_EXT3) {
+ if ((feature_bits & FEATURE_WRSR_EXT3) == FEATURE_WRSR_EXT3) {
if (spi_prepare_wrsr_ext(write_cmd, &write_cmd_len, flash, reg, value))
return 1;
break;
@@ -188,7 +188,8 @@ int spi_read_register(const struct flashctx *flash, enum flash_reg reg, uint8_t
msg_cerr("Cannot read SR2: unsupported by chip\n");
return 1;
case STATUS3:
- if (feature_bits & (FEATURE_WRSR_EXT3 | FEATURE_WRSR3)) {
+ if ((feature_bits & FEATURE_WRSR_EXT3) == FEATURE_WRSR_EXT3
+ || (feature_bits & FEATURE_WRSR3)) {
read_cmd = JEDEC_RDSR3;
break;
}