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authorEdward O'Callaghan <quasisec@google.com>2020-04-12 17:27:53 +1000
committerAngel Pons <th3fanbus@gmail.com>2020-04-30 08:00:41 +0000
commite4ddc36371bc07c71889f21f9144160c756e9825 (patch)
tree013c09671b5c91189b9e75f684180252d3ef98e4 /wbsio_spi.c
parente0272e2b6f8860152d0edf72263a80426fd7d5e3 (diff)
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const'ify flashctx to align signatures with cros flashrom
The ChromiumOS flashrom fork has since const'ify flashctx in a few places. This aligns the function signatures to match with downstream to ease forward porting patches out of downstream back into mainline flashrom. This patch is minimum viable alignment and so feedback is welcome. Change-Id: Iff6dbda13cb0d941481c0d204b9c30895630fbd1 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40324 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'wbsio_spi.c')
-rw-r--r--wbsio_spi.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/wbsio_spi.c b/wbsio_spi.c
index f4f6af905..1674825e2 100644
--- a/wbsio_spi.c
+++ b/wbsio_spi.c
@@ -57,7 +57,7 @@ done:
return flashport;
}
-static int wbsio_spi_send_command(struct flashctx *flash, unsigned int writecnt,
+static int wbsio_spi_send_command(const struct flashctx *flash, unsigned int writecnt,
unsigned int readcnt,
const unsigned char *writearr,
unsigned char *readarr);
@@ -110,7 +110,7 @@ int wbsio_check_for_spi(void)
* Would one more byte of RAM in the chip (to get all 24 bits) really make
* such a big difference?
*/
-static int wbsio_spi_send_command(struct flashctx *flash, unsigned int writecnt,
+static int wbsio_spi_send_command(const struct flashctx *flash, unsigned int writecnt,
unsigned int readcnt,
const unsigned char *writearr,
unsigned char *readarr)