diff options
| -rw-r--r-- | include/flash.h | 4 | ||||
| -rw-r--r-- | include/spi.h | 5 | ||||
| -rw-r--r-- | spi25_statusreg.c | 24 |
3 files changed, 33 insertions, 0 deletions
diff --git a/include/flash.h b/include/flash.h index 197c11ea1..23222c722 100644 --- a/include/flash.h +++ b/include/flash.h @@ -161,6 +161,9 @@ enum write_granularity { */ #define FEATURE_SCUR (1 << 24) +/* Whether chip has configuration register (RDCR/WRSR_EXT2 commands) */ +#define FEATURE_CFGR (1 << 25) + #define ERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0x00 : 0xff) #define UNERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0xff : 0x00) @@ -196,6 +199,7 @@ enum flash_reg { STATUS2, STATUS3, SECURITY, + CONFIG, MAX_REGISTERS }; diff --git a/include/spi.h b/include/spi.h index c77866c41..505aecd01 100644 --- a/include/spi.h +++ b/include/spi.h @@ -177,6 +177,11 @@ #define JEDEC_WRSCUR_OUTSIZE 0x01 #define JEDEC_WRSCUR_INSIZE 0x00 +/* Read Configuration Register */ +#define JEDEC_RDCR 0x15 +#define JEDEC_RDCR_OUTSIZE 0x01 +#define JEDEC_RDCR_INSIZE 0x01 + /* Enter 4-byte Address Mode */ #define JEDEC_ENTER_4_BYTE_ADDR_MODE 0xB7 diff --git a/spi25_statusreg.c b/spi25_statusreg.c index 2859b2320..b178b2e37 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -107,6 +107,23 @@ int spi_write_register(const struct flashctx *flash, enum flash_reg reg, uint8_t */ msg_cerr("Cannot write SECURITY: unsupported by design\n"); return 1; + case CONFIG: + /* + * This one is read via a separate command, but written as if it's SR2 + * in FEATURE_WRSR_EXT2 case of WRSR command. + */ + if (feature_bits & FEATURE_CFGR) { + write_cmd[0] = JEDEC_WRSR; + if (spi_read_register(flash, STATUS1, &write_cmd[1])) { + msg_cerr("Writing CONFIG failed: failed to read SR1 for writeback.\n"); + return 1; + } + write_cmd[2] = value; + write_cmd_len = 3; + break; + } + msg_cerr("Cannot write CONFIG: unsupported by chip\n"); + return 1; default: msg_cerr("Cannot write register: unknown register\n"); return 1; @@ -209,6 +226,13 @@ int spi_read_register(const struct flashctx *flash, enum flash_reg reg, uint8_t } msg_cerr("Cannot read SECURITY: unsupported by chip\n"); return 1; + case CONFIG: + if (feature_bits & FEATURE_CFGR) { + read_cmd = JEDEC_RDCR; + break; + } + msg_cerr("Cannot read CONFIG: unsupported by chip\n"); + return 1; default: msg_cerr("Cannot read register: unknown register\n"); return 1; |