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diff --git a/doc/about_flashrom/index.rst b/doc/about_flashrom/index.rst
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@@ -0,0 +1,7 @@
+About flashrom
+==============
+
+.. toctree::
+ :maxdepth: 1
+
+ team
diff --git a/doc/about_flashrom/team.rst b/doc/about_flashrom/team.rst
new file mode 100644
index 000000000..9d002bb66
--- /dev/null
+++ b/doc/about_flashrom/team.rst
@@ -0,0 +1,61 @@
+=========
+Team
+=========
+
+flashrom development process is happening in Gerrit.
+All contributors and users who have a Gerrit account can send patches,
+add comments to patches and vote +1..-1 on patches.
+
+All contributors and users are expected to follow Development guidelines,
+Code of Conduct and Friendliness guidelines.
+
+There are two special groups in Gerrit.
+
+"flashrom reviewers" group
+==========================
+
+Members of the group can do full approval of patches (i.e. vote +2).
+
+In general, members of the group have some area of responsibility in the MAINTAINERS file,
+and are automatically added as reviewers to patches when the patch touches this area.
+
+The responsibilities are the following.
+
+* React to patches when added as a reviewer.
+
+* Try to respond to technical questions on the mailing list if the topic is something you know about
+ and can provide a useful response.
+
+* Know development guidelines and check the patches you are reviewing align with the guidelines.
+
+"flashrom developers" group
+===========================
+
+Members of the group can merge patches.
+The responsibilities for the members of the group are described in more details below.
+
+There is no expectation on how much time you spend on your duties, some non-zero amount of time,
+whatever capacity you have. But in general, you stay around on flashrom.
+
+If you disappear for some time (life happens), especially for a longer time, like several months,
+especially without a warning: you implicitly agree that the others will handle the duties and make decisions if needed
+(potentially without waiting for you to come back, if the decision is needed quickly).
+
+* Merge all contributors's patches (when they are ready), not just your own.
+
+* Be at least vaguely aware what development efforts are ongoing, this helps to make decisions
+ in what order the patches should be merged, and where could be merge conflicts.
+
+* Know development guidelines, and educate other contributors if needed (e.g. give links).
+
+* React to patches when added as a reviewer.
+
+* Try to respond to technical questions on the mailing list if the topic is something you know about
+ and can provide a useful response.
+
+* From time to time show up in real-time channel(s) and/or dev meetings.
+
+* Follow the Code of Conduct and Friendliness guidelines, be a good example for others.
+
+* Bonus point: if you work in a [software] company, educate and help contributors from your company
+ with upstream culture and dev guidelines.
diff --git a/doc/classic_cli_manpage.rst b/doc/classic_cli_manpage.rst
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+Manual page
+===========
+
+
+NAME
+----
+
+**flashrom** - detect, read, write, verify and erase flash chips
+
+
+SYNOPSIS
+--------
+
+| **flashrom** [-h|-R|-L|-z|
+| -p <programmername>[:<parameters>] [-c <chipname>]
+| (--flash-name|--flash-size|
+| [-E|-x|-r <file>|-w <file>|-v <file>]
+| [(-l <file>|--ifd|--fmap|--fmap-file <file>)
+| [-i <include>[:<file>]]]
+| [--wp-status] [--wp-list] [--wp-enable|--wp-disable]
+| [--wp-range <start>,<length>|--wp-region <region>]
+| [-n] [-N] [-f])]
+| [-V[V[V]]] [-o <logfile>] [--progress]
+
+
+DESCRIPTION
+-----------
+
+**flashrom** is a utility for detecting, reading, writing, verifying and erasing flash chips.
+It's often used to flash BIOS/EFI/coreboot/firmware images in-system using a supported mainboard.
+However, it also supports various external PCI/USB/parallel-port/serial-port based devices which can program flash
+chips, including some network cards (NICs), SATA/IDE controller cards, graphics cards, the Bus Pirate device,
+various FTDI FT2232/FT4232H/FT4233H/FT232H based USB devices, and more.
+
+It supports a wide range of DIP32, PLCC32, DIP8, SO8/SOIC8, TSOP32, TSOP40, TSOP48, and BGA chips,
+which use various protocols such as LPC, FWH, parallel flash, or SPI.
+
+
+OPTIONS
+-------
+
+You can specify one of ``-h``, ``-R``, ``-L``, ``-z``, ``-E``, ``-r``, ``-w``, ``-v`` or no operation.
+If no operation is specified, **flashrom** will only probe for flash chips. It is recommended that if you try **flashrom** the
+first time on a system, you run it in probe-only mode and check the output.
+Also you are advised to make a backup of your current ROM contents with ``-r`` before you try to write a new image.
+All operations involving any chip access (probe/read/write/...) require the ``-p/--programmer`` option to be used (please see below).
+
+
+**-r, --read <file>**
+ Read flash ROM contents and save them into the given **<file>**.
+ If the file already exists, it will be overwritten.
+
+
+**-w, --write (<file>|-)**
+ Write **<file>** into flash ROM. If **-** is provided instead, contents will be read from stdin.
+ This will first automatically erase the chip, then write to it.
+
+ In the process the chip is also read several times. First an in-memory backup is made for disaster recovery and to be
+ able to skip regions that are already equal to the image file.
+ This copy is updated along with the write operation. In case of erase errors it is even re-read completely.
+ After writing has finished and if verification is enabled, the whole flash chip is read out and compared with the input image.
+
+
+**-n, --noverify**
+ Skip the automatic verification of flash ROM contents after writing. Using this option is **not** recommended,
+ you should only use it if you know what you are doing and if you feel that the time for verification takes too long.
+
+ Typical usage is::
+
+ flashrom -p prog -n -w <file>
+
+ This option is only useful in combination with ``--write``.
+
+
+**-N, --noverify-all**
+ Skip not included regions during automatic verification after writing (cf. ``-l`` and ``-i``).
+ You should only use this option if you are sure that communication with the flash chip is reliable
+ (e.g. when using the **internal** programmer).
+ Even if **flashrom** is instructed not to touch parts of the flash chip, their contents could be damaged
+ (e.g. due to misunderstood erase commands).
+
+ This option is required to flash an Intel system with locked ME flash region using the **internal** programmer.
+ It may be enabled by default in this case in the future.
+
+
+**-v, --verify (<file>|-)**
+ Verify the flash ROM contents against the given **<file>**.
+ If **-** is provided instead, contents will be written to the stdout.
+
+
+**-E, --erase**
+ Erase the flash ROM chip.
+
+
+**-x, --extract**
+ Extract every region defined on the layout from flash ROM chip to a file with the same name as the extracted region
+ (replacing spaces with underscores).
+
+
+**-V, --verbose**
+ More verbose output. This option can be supplied multiple times (max. 3 times, i.e. ``-VVV`` ) for even more debug output.
+
+
+**-c, --chip <chipname>**
+ Probe only for the specified flash ROM chip. This option takes the chip name as printed by ``flashrom -L`` without the
+ vendor name as parameter. Please note that the chip name is case sensitive.
+
+
+**-f, --force**
+ Force one or more of the following actions:
+
+ * Force chip read and pretend the chip is there.
+ * Force chip access even if the chip is bigger than the maximum supported size for the flash bus.
+ * Force erase even if erase is known bad.
+ * Force write even if write is known bad.
+
+
+**-l, --layout <file>**
+ Read ROM layout from **<file>**.
+
+ **flashrom** supports ROM layouts. This allows you to flash certain parts of the flash chip only.
+ A ROM layout file contains multiple lines with the following syntax::
+
+ startaddr:endaddr imagename
+
+ ``startaddr`` and ``endaddr`` are hexadecimal addresses within the ROM file and do not refer to any physical address.
+ Please note that using a 0x prefix for those hexadecimal numbers is not necessary, but you can't specify decimal/octal numbers.
+ ``imagename`` is an arbitrary name for the region/image from ``startaddr`` to ``endaddr`` (both addresses included).
+
+ Example::
+
+ 00000000:00008fff gfxrom
+ 00009000:0003ffff normal
+ 00040000:0007ffff fallback
+
+ If you only want to update the image named **normal** in a ROM based on the layout above, run::
+
+ flashrom -p prog --layout rom.layout --image normal -w some.rom
+
+ To update only the images named **normal** and **fallback**, run::
+
+ flashrom -p prog -l rom.layout -i normal -i fallback -w some.rom
+
+ Overlapping sections are not supported.
+
+
+**--fmap**
+ Read layout from fmap in flash chip.
+
+ **flashrom** supports the fmap binary format which is commonly used by coreboot for partitioning a flash chip.
+ The on-chip fmap will be read and used to generate the layout.
+
+ If you only want to update the **COREBOOT** region defined in the fmap, run::
+
+ flashrom -p prog --fmap --image COREBOOT -w some.rom
+
+
+**--fmap-file <file>**
+ Read layout from a **<file>** containing binary fmap (e.g. coreboot roms).
+
+ **flashrom** supports the fmap binary format which is commonly used by coreboot for partitioning a flash chip.
+ The fmap in the specified file will be read and used to generate the layout.
+
+ If you only want to update the **COREBOOT** region defined in the binary fmap file, run::
+
+ flashrom -p prog --fmap-file some.rom --image COREBOOT -w some.rom
+
+
+**--ifd**
+ Read ROM layout from Intel Firmware Descriptor.
+
+ **flashrom** supports ROM layouts given by an Intel Firmware Descriptor (IFD).
+ The on-chip descriptor will be read and used to generate the layout. If you need to change the layout,
+ you have to update the IFD only first.
+
+ The following ROM images may be present in an IFD:
+
+ | ``fd`` - the IFD itself
+ | ``bios`` - the host firmware aka. BIOS
+ | ``me`` - Intel Management Engine firmware
+ | ``gbe`` - gigabit ethernet firmware
+ | ``pd`` - platform specific data
+
+
+**-i, --include <region>[:<file>]**
+ Read or write only **<region>** to or from ROM.
+ The **-i** option may be used multiple times if the user wishes to read or write multiple regions using a single command.
+
+ The user may optionally specify a corresponding **<file>** for any region they wish to read or write.
+ A read operation will read the corresponding regions from ROM and write individual files for each one.
+ A write option will read file(s) and write to the corresponding region(s) in ROM.
+
+ For write operations, files specified using ``-i`` take precedence over content from the argument to ``-w``.
+
+ Examples:
+ To read regions named **foo** and **bar** in layout file **<layout>** into region-sized files **foo.bin** and **bar.bin**, run::
+
+ flashrom -p prog -l <layout> -i foo:foo.bin -i bar:bar.bin -r rom.bin
+
+ To write files **foo.bin** and **bar.bin** into regions named **foo** and **bar** in layout file **<layout>** to the ROM, run::
+
+ flashrom -p prog -l <layout> -i foo:foo.bin -i bar:bar.bin -w rom.bin
+
+
+**--wp-status**
+ Prints the flash's current status register protection mode and write protection range.
+
+
+**--wp-list**
+ Prints a list of all protection ranges that the flash supports.
+
+
+**--wp-enable**
+ Enables hardware status register protection (SRP) if the flash supports it.
+ Once SRP is enabled, operations that change the flash's status registers (including ``--wp-disable`` and ``--wp-range``)
+ can only be performed if the flash's #WP pin is at an inactive logic level.
+
+
+**--wp-disable**
+ Disables status register protection if the flash allows it.
+
+
+**--wp-range <start>,<length>**
+ Configures the flash to protect a range of addresses from <start> to (<start> + <length> - 1), bounds inclusive.
+ The range must be supported by the flash, see ``--wp-list``.
+
+
+**--wp-region <region>**
+ Same as ``--wp-range`` but protects the range occupied by an image region.
+ This option requires a image layout to be specified, see ``--layout``.
+ The region must be supported by the flash, see ``--wp-list``.
+
+
+**--flash-name**
+ Prints out the detected flash chip's name.
+
+
+**--flash-size**
+ Prints out the detected flash chip's size.
+
+
+**--flash-contents <ref-file>**
+ The file contents of **<ref-file>** will be used to decide which parts of the flash need to be written.
+ Providing this saves an initial read of the full flash chip.
+ Be careful, if the provided data doesn't actually match the flash contents, results are undefined.
+
+
+**-L, --list-supported**
+ List the flash chips, chipsets, mainboards, and external programmers (including PCI, USB, parallel port, and serial port based devices)
+ supported by **flashrom**.
+
+ There are many unlisted boards which will work out of the box, without special support in **flashrom**.
+ Please let us know if you can verify that other boards work or do not work out of the box.
+
+ **IMPORTANT**:
+ For verification you have to test an ERASE and/or WRITE operation, so make sure you only do that if you have proper means to recover from failure!
+
+
+**-z, --list-supported-wiki**
+ Same as ``--list-supported``, but outputs the supported hardware in MediaWiki syntax,
+ so that it can be easily pasted into the `supported hardware wiki page <https://flashrom.org/Supported_hardware>`_.
+ Please note that MediaWiki output is not compiled in by default.
+
+
+**-p, --programmer <name>[:parameter[,parameter[,parameter]]]**
+ Specify the programmer device. This is mandatory for all operations involving any chip access (probe/read/write/...).
+ Currently supported are:
+
+ * ``internal`` (for in-system flashing in the mainboard)
+ * ``dummy`` (virtual programmer for testing **flashrom**)
+ * ``nic3com`` (for flash ROMs on 3COM network cards)
+ * ``nicrealtek`` (for flash ROMs on Realtek and SMC 1211 network cards)
+ * ``nicnatsemi`` (for flash ROMs on National Semiconductor DP838* network cards)
+ * ``nicintel`` (for parallel flash ROMs on Intel 10/100Mbit network cards)
+ * ``gfxnvidia`` (for flash ROMs on NVIDIA graphics cards)
+ * ``drkaiser`` (for flash ROMs on Dr. Kaiser PC-Waechter PCI cards)
+ * ``satasii`` (for flash ROMs on Silicon Image SATA/IDE controllers)
+ * ``satamv`` (for flash ROMs on Marvell SATA controllers)
+ * ``atahpt`` (for flash ROMs on Highpoint ATA/RAID controllers)
+ * ``atavia`` (for flash ROMs on VIA VT6421A SATA controllers)
+ * ``atapromise`` (for flash ROMs on Promise PDC2026x ATA/RAID controllers)
+ * ``it8212`` (for flash ROMs on ITE IT8212F ATA/RAID controller)
+ * ``ft2232_spi`` (for SPI flash ROMs attached to an FT2232/FT4232H/FT232H family based USB SPI programmer)
+ * ``serprog`` (for flash ROMs attached to a programmer speaking serprog, including some Arduino-based devices)
+ * ``buspirate_spi`` (for SPI flash ROMs attached to a Bus Pirate)
+ * ``dediprog`` (for SPI flash ROMs attached to a Dediprog SF100)
+ * ``rayer_spi`` (for SPI flash ROMs attached to a parallel port by one of various cable types)
+ * ``raiden_debug_spi`` (For Chrome EC based debug tools - SuzyQable, Servo V4, C2D2 & uServo)
+ * ``pony_spi`` (for SPI flash ROMs attached to a SI-Prog serial port bitbanging adapter)
+ * ``nicintel_spi`` (for SPI flash ROMs on Intel Gigabit network cards)
+ * ``ogp_spi`` (for SPI flash ROMs on Open Graphics Project graphics card)
+ * ``linux_mtd`` (for SPI flash ROMs accessible via /dev/mtdX on Linux)
+ * ``linux_spi`` (for SPI flash ROMs accessible via /dev/spidevX.Y on Linux)
+ * ``usbblaster_spi`` (for SPI flash ROMs attached to an Altera USB-Blaster compatible cable)
+ * ``nicintel_eeprom`` (for SPI EEPROMs on Intel Gigabit network cards)
+ * ``mstarddc_spi`` (for SPI flash ROMs accessible through DDC in MSTAR-equipped displays)
+ * ``pickit2_spi`` (for SPI flash ROMs accessible via Microchip PICkit2)
+ * ``ch341a_spi`` (for SPI flash ROMs attached to WCH CH341A)
+ * ``ch347_api`` (for SPI flash ROMs attached to WHC CH347)
+ * ``digilent_spi`` (for SPI flash ROMs attached to iCEblink40 development boards)
+ * ``jlink_spi`` (for SPI flash ROMs attached to SEGGER J-Link and compatible devices)
+ * ``ni845x_spi`` (for SPI flash ROMs attached to National Instruments USB-8451 or USB-8452)
+ * ``stlinkv3_spi`` (for SPI flash ROMs attached to STMicroelectronics STLINK V3 devices)
+ * ``realtek_mst_i2c_spi`` (for SPI flash ROMs attached to Realtek DisplayPort hubs accessible through I2C)
+ * ``parade_lspcon`` (for SPI flash ROMs attached to Parade Technologies LSPCONs (PS175))
+ * ``mediatek_i2c_spi`` (for SPI flash ROMs attached to some Mediatek display devices accessible over I2C)
+ * ``dirtyjtag_spi`` (for SPI flash ROMs attached to DirtyJTAG-compatible devices)
+ * ``asm106x`` (for SPI flash ROMs attached to asm106x PCI SATA controllers)
+
+ Some programmers have optional or mandatory parameters which are described in detail in the
+ **PROGRAMMER-SPECIFIC INFORMATION** section. Support for some programmers can be disabled at compile time.
+ ``flashrom -h`` lists all supported programmers.
+
+
+**-h, --help**
+ Show a help text and exit.
+
+
+**-o, --output <logfile>**
+ Save the full debug log to **<logfile>**.
+ If the file already exists, it will be overwritten. This is the recommended way to gather logs from **flashrom**
+ because they will be verbose even if the on-screen messages are not verbose and don't require output redirection.
+
+
+**--progress**
+ [Experimental feature] Show progress percentage of operations on the standard output.
+
+
+**-R, --version**
+ Show version information and exit.
+
+
+PROGRAMMER-SPECIFIC INFORMATION
+-------------------------------
+Some programmer drivers accept further parameters to set programmer-specific parameters. These parameters are separated
+from the programmer name by a colon. While some programmers take arguments atfixed positions, other programmers use a
+key/value interface in which the key and value is separated by an equal sign and different pairs are separated by a
+comma or a colon.
+
+
+internal programmer
+^^^^^^^^^^^^^^^^^^^
+
+
+**Board Enables**
+ Some mainboards require to run mainboard specific code to enable flash erase and write support
+ (and probe support on old systems with parallel flash).
+ The mainboard brand and model (if it requires specific code) is usually autodetected using one of the following mechanisms:
+ If your system is running coreboot, the mainboard type is determined from the coreboot table.
+ Otherwise, the mainboard is detected by examining the onboard PCI devices and possibly DMI info.
+ If PCI and DMI do not contain information to uniquely identify the mainboard (which is the exception),
+ or if you want to override the detected mainboard model, you can specify the mainboard using the::
+
+ flashrom -p internal:mainboard=<vendor>:<board>
+
+ syntax.
+
+ See the **Known boards** or **Known laptops** section in the output of ``flashrom -L`` for a list of boards
+ which require the specification of the board name, if no coreboot table is found.
+
+ Some of these board-specific flash enabling functions (called **board enables** ) in **flashrom** have not yet been tested.
+ If your mainboard is detected needing an untested board enable function, a warning message is printed and the board enableis not executed,
+ because a wrong board enable function might cause the system to behave erratically, as board enable functions touch the
+ low-level internals of a mainboard.
+ Not executing a board enable function (if one is needed) might cause detection or erasing failure.
+ If your board protects only part of the flash (commonly the top end, called boot block),
+ **flashrom** might encounter an error only after erasing the unprotected part, so running without the board-enable function
+ might be dangerous for erase and write (which includes erase).
+
+ The suggested procedure for a mainboard with untested board specific code is to first try to probe the ROM
+ (just invoke **flashrom** and check that it detects your flash chip type) without running the board enable code
+ (i.e. without any parameters). If it finds your chip, fine. Otherwise, retry probing your chip with the board-enable code running, using::
+
+ flashrom -p internal:boardenable=force
+
+ If your chip is still not detected, the board enable code seems to be broken or the flash chip unsupported.
+ Otherwise, make a backup of your current ROM contents (using ``-r``) and store it to a medium outside of your computer,
+ like a USB drive or a network share. If you needed to run the board enable code already for probing, use it for reading too.
+ If reading succeeds and the contents of the read file look legit you can try to write the new image.
+ You should enable the board enable code in any case now, as it has been written because it is known that writing/erasing
+ without the board enable is going to fail. In any case (success or failure), please report to the **flashrom** mailing list, see below.
+
+**Coreboot**
+ On systems running coreboot, **flashrom** checks whether the desired image matches your mainboard.
+ This needs some special board ID to be present in the image.
+ If **flashrom** detects that the image you want to write and the current board do not match,
+ it will refuse to write the image unless you specify::
+
+ flashrom -p internal:boardmismatch=force
+
+
+**ITE IT87 Super I/O**
+ If your mainboard is manufactured by GIGABYTE and supports DualBIOS it is very likely that it uses an
+ ITE IT87 series Super I/O to switch between the two flash chips.
+ Only one of them can be accessed at a time and you can manually select which one to use with the::
+
+ flashrom -p internal:dualbiosindex=chip
+
+ syntax where ``chip`` is the index of the chip to use (0 = main, 1 = backup).
+ You can check which one is currently selected by leaving out the ``chip`` parameter.
+
+ If your mainboard uses an ITE IT87 series Super I/O for LPC<->SPI flash bus translation, **flashrom** should autodetect that configuration.
+ If you want to set the I/O base port of the IT87 series SPI controller manually instead of using the value provided by the BIOS,
+ use the::
+
+ flashrom -p internal:it87spiport=portnum
+
+ syntax where ``portnum`` is the I/O port number (must be a multiple of 8).
+ In the unlikely case **flashrom** doesn't detect an active IT87 LPC<->SPI bridge, please send a bug report so we can diagnose the problem.
+
+
+**AMD chipsets**
+ Beginning with the SB700 chipset there is an integrated microcontroller (IMC) based on the 8051 embedded in every AMD southbridge.
+ Its firmware resides in the same flash chip as the host's which makes writing to the flash risky if the IMC is active.
+ Flashrom tries to temporarily disable the IMC but even then changing the contents of the flash can have unwanted effects:
+ when the IMC continues (at the latest after a reboot) it will continue executing code from the flash.
+ If the code was removed or changed in an unfortunate way it is unpredictable what the IMC will do.
+ Therefore, if **flashrom** detects an active IMC it will disable write support unless the user forces it with the::
+
+ flashrom -p internal:amd_imc_force=yes
+
+ syntax. The user is responsible for supplying a suitable image or leaving out the IMC region with the help of a layout file.
+ This limitation might be removed in the future when we understand the details better and have received enough feedback from users.
+ Please report the outcome if you had to use this option to write a chip.
+
+ An optional ``spispeed`` parameter specifies the frequency of the SPI bus where applicable
+ (i.e.SB600 or later with an SPI flash chip directly attached to the chipset).
+ Syntax is::
+
+ flashrom -p internal:spispeed=frequency
+
+ where ``frequency`` can be ``'16.5 MHz'``, ``'22 MHz'``, ``'33 MHz'``, ``'66 MHz'``, ``'100 MHZ'``, or ``'800 kHz'``.
+ Support of individual frequencies depends on the generation of the chipset:
+
+ * SB6xx, SB7xx, SP5xxx: from 16.5 MHz up to and including 33 MHz.
+ The default is to use 16.5 MHz and disable Fast Reads.
+ * SB8xx, SB9xx, Hudson: from 16.5 MHz up to and including 66 MHz.
+ The default is to use 16.5 MHz and disable Fast Reads.
+ * Yangtze (with SPI 100 engine as found in Kabini and Tamesh): all of them.
+ The default is to use the frequency that is currently configured.
+
+ An optional ``spireadmode`` parameter specifies the read mode of the SPI bus where applicable (Bolton or later).
+ Syntax is::
+
+ flashrom -p internal:spireadmode=mode
+
+ where ``mode`` can be ``'Normal (up to 33 MHz)'``, ``'Normal (up to 66 MHz)'``, ``'Dual IO (1-1-2)'``, ``'Quad IO (1-1-4)'``,
+ ``'Dual IO (1-2-2)'``, ``'Quad IO (1-4-4)'``, or ``'Fast Read'``.
+
+ The default is to use the read mode that is currently configured.
+
+
+**Intel chipsets**
+ If you have an Intel chipset with an ICH8 or later southbridge with SPI flash attached, and if a valid descriptor was written
+ to it (e.g. by the vendor), the chipset provides an alternative way to access the flash chip(s) named **Hardware Sequencing**.
+ It is much simpler than the normal access method (called **Software Sequencing**), but does not allow the software to
+ choose the SPI commands to be sent. You can use the::
+
+ flashrom -p internal:ich_spi_mode=value
+
+ syntax where ``value`` can be ``auto``, ``swseq`` or ``hwseq``. By default (or when setting ``ich_spi_mode=auto``) the
+ module tries to use swseq and only activates hwseq if need be (e.g. if important opcodes are inaccessible due to lockdown;
+ or if more than one flash chip is attached). The other options (swseq, hwseq) select the respective mode (if possible).
+
+ ICH8 and later southbridges may also have locked address ranges of different kinds if a valid descriptor was written to it.
+ The flash address space is then partitioned in multiple so called "Flash Regions" containing the host firmware,
+ the ME firmware and so on respectively. The flash descriptor can also specify up to 5 so called **Protected Regions**,
+ which are freely chosen address ranges independent from the aforementioned **Flash Regions**.
+ All of them can be write and/or read protected individually.
+
+ If you have an Intel chipset with an ICH2 or later southbridge and if you want to set specific IDSEL values for a
+ non-default flash chip or an embedded controller (EC), you can use the::
+
+ flashrom -p internal:fwh_idsel=value
+
+ syntax where ``value`` is the 48-bit hexadecimal raw value to be written in the IDSEL registers of the Intel southbridge.
+ The upper 32 bits use one hex digit each per 512 kB range between 0xffc00000 and 0xffffffff, and the lower 16 bits
+ use one hex digit each per 1024 kB range between 0xff400000 and 0xff7fffff.
+ The rightmost hex digit corresponds with the lowest address range. All address ranges have a corresponding sister range
+ 4 MB below with identical IDSEL settings. The default value for ICH7 is given in the example below.
+
+ Example::
+
+ flashrom -p internal:fwh_idsel=0x001122334567
+
+
+**Laptops**
+ Using **flashrom** on older laptops that don't boot from the SPI bus is dangerous and may easily make your hardware unusable
+ (see also the **BUGS** section). The embedded controller (EC) in some machines may interact badly with flashing.
+ More information is `in the wiki <https://flashrom.org/Laptops>`_.
+ Problems occur when the flash chip is shared between BIOS and EC firmware, and the latter does not expect **flashrom**
+ to access the chip. While **flashrom** tries to change the contents of that memory the EC might need to fetch new
+ instructions or data from it and could stop working correctly. Probing for and reading from the chip may also irritate
+ your EC and cause fan failure, backlight failure, sudden poweroff, and other nasty effects. **flashrom** will attempt to
+ detect if it is running on such a laptop and limit probing to SPI buses. If you want to probe the LPC bus anyway at your own risk, use::
+
+ flashrom -p internal:laptop=force_I_want_a_brick
+
+ We will not help you if you force flashing on a laptop because this is a really dumb idea.
+
+ You have been warned.
+
+ Currently we rely on the chassis type encoded in the DMI/SMBIOS data to detect laptops. Some vendors did not implement
+ those bits correctly or set them to generic and/or dummy values. **flashrom** will then issue a warning and restrict buses like above.
+ In this case you can use::
+
+ flashrom -p internal:laptop=this_is_not_a_laptop
+
+ to tell **flashrom** (at your own risk) that it is not running on a laptop.
+
+
+dummy programmer
+^^^^^^^^^^^^^^^^
+
+The dummy programmer operates on a buffer in memory only. It provides a safe and fast way to test various aspects of
+**flashrom** and is mainly used in development and while debugging.
+It is able to emulate some chips to a certain degree (basic identify/read/erase/write operations work).
+
+An optional parameter specifies the bus types it should support. For that you have to use the::
+
+ flashrom -p dummy:bus=[type[+type[+type]]]
+
+syntax where ``type`` can be ``parallel``, ``lpc``, ``fwh``, ``spi`` in any order. If you specify bus without type,
+all buses will be disabled. If you do not specify bus, all buses will be enabled.
+
+Example::
+
+ flashrom -p dummy:bus=lpc+fwh
+
+The dummy programmer supports flash chip emulation for automated self-tests without hardware access.
+If you want to emulate a flash chip, use the::
+
+ flashrom -p dummy:emulate=chip
+
+syntax where ``chip`` is one of the following chips (please specify only the chip name, not the vendor):
+
+* ST ``M25P10.RES`` SPI flash chip (128 kB, RES, page write)
+* SST ``SST25VF040.REMS`` SPI flash chip (512 kB, REMS, byte write)
+* SST ``SST25VF032B`` SPI flash chip (4096 kB, RDID, AAI write)
+* Macronix ``MX25L6436`` SPI flash chip (8192 kB, RDID, SFDP)
+* Winbond ``W25Q128FV`` SPI flash chip (16384 kB, RDID)
+* Spansion ``S25FL128L`` SPI flash chip (16384 kB, RDID)
+* Dummy vendor ``VARIABLE_SIZE`` SPI flash chip (configurable size, page write)
+
+Example::
+
+ flashrom -p dummy:emulate=SST25VF040.REMS
+
+To use ``VARIABLE_SIZE`` chip, ``size`` must be specified to configure the size of the flash chip as a power of two.
+
+Example::
+
+ flashrom -p dummy:emulate=VARIABLE_SIZE,size=16777216,image=dummy.bin
+
+
+**Persistent images**
+ If you use flash chip emulation, flash image persistence is available as well by using the::
+
+ flashrom -p dummy:emulate=chip,image=image.rom
+
+ syntax where ``image.rom`` is the file where the simulated chip contents are read on **flashrom** startup and where the
+ chip contents on **flashrom** shutdown are written to.
+
+ Example::
+
+ flashrom -p dummy:emulate=M25P10.RES,image=dummy.bin
+
+
+**SPI write chunk size**
+ If you use SPI flash chip emulation for a chip which supports SPI page write with the default opcode,
+ you can set the maximum allowed write chunk size with the::
+
+ flashrom -p dummy:emulate=chip,spi_write_256_chunksize=size
+
+ syntax where ``size`` is the number of bytes (min.\& 1, max.\& 256).
+ Example::
+
+ flashrom -p dummy:emulate=M25P10.RES,spi_write_256_chunksize=5
+
+
+**SPI blacklist**
+ To simulate a programmer which refuses to send certain SPI commands to the flash chip, you can specify a blacklist of
+ SPI commands with the::
+
+ flashrom -p dummy:spi_blacklist=commandlist
+
+ syntax where ``ommandlist`` is a list of two-digit hexadecimal representations of SPI commands.
+ If commandlist is e.g. 0302, **flashrom** will behave as if the SPI controller refuses to run command 0x03 (READ) and command 0x02 (WRITE).
+ commandlist may be up to 512 characters (256 commands) long.
+ Implementation note: **flashrom** will detect an error during command execution.
+
+
+**SPI ignorelist**
+ To simulate a flash chip which ignores (doesn't support) certain SPI commands, you can specify an ignorelist of SPI commands with the::
+
+ flashrom -p dummy:spi_ignorelist=commandlist
+
+ syntax where ``commandlist`` is a list of two-digit hexadecimal representations of SPI commands.
+ If commandlist is e.g. 0302, the emulated flash chip will ignore command 0x03 (READ) and command 0x02 (WRITE).
+ ``commandlist`` may be up to 512 characters (256 commands) long.
+ Implementation note: **flashrom** won't detect an error during command execution.
+
+
+**SPI status register**
+ You can specify the initial content of the chip's status register with the::
+
+ flashrom -p dummy:spi_status=content"
+
+ syntax where ``content`` is a hexadecimal value of up to 24 bits. For example, ``0x332211`` assigns 0x11 to SR1,
+ 0x22 to SR2 and 0x33 to SR3. Shorter value is padded to 24 bits with zeroes on the left.
+ See datasheet for chosen chip for details about the registers content.
+
+
+**Write protection**
+ Chips with emulated WP: **W25Q128FV**, **S25FL128L**.
+
+ You can simulate state of hardware protection pin (WP) with the::
+
+ flashrom -p dummy:hwwp=state
+
+ syntax where ``state`` is ``yes`` or ``no`` (default value). ``yes`` means active state of the pin implies that chip is
+ write-protected (on real hardware the pin is usually negated, but not here).
+
+
+nic3com, nicrealtek, nicnatsemi, nicintel, nicintel_eeprom, nicintel_spi, gfxnvidia, ogp_spi, drkaiser, satasii, satamv, atahpt, atavia, atapromise, it8212 programmers
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+These programmers have an option to specify the PCI address of the card your want to use, which must be specified if
+more than one card supported by the selected programmer is installed in your system. The syntax is::
+
+ flashrom -p xxxx:pci=bb:dd.f
+
+where ``xxxx`` is the name of the programmer, ``bb`` is the PCI bus number, ``dd`` is the PCI device number, and ``b``
+is the PCI function number of the desired device. Example::
+
+ flashrom -p nic3com:pci=05:04.0
+
+
+atavia programmer
+^^^^^^^^^^^^^^^^^
+
+Due to the mysterious address handling of the VIA VT6421A controller the user can specify an offset with the::
+
+ flashrom -p atavia:offset=addr
+
+syntax where ``addr`` will be interpreted as usual (leading 0x (0) for hexadecimal (octal) values, or else decimal).
+For more information please see `its wiki page <https://flashrom.org/VT6421A "its wiki page>`_.
+
+
+atapromise programmer
+^^^^^^^^^^^^^^^^^^^^^
+
+This programmer is currently limited to 32 kB, regardless of the actual size of the flash chip. This stems from the
+fact that, on the tested device (a Promise Ultra100), not all of the chip's address lines were actually connected.
+You may use this programmer to flash firmware updates, since these are only 16 kB in size (padding to 32 kB is required).
+
+
+nicintel_eeprom programmer
+^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+This is the first programmer module in **flashrom** that does not provide access to NOR flash chips but EEPROMs mounted on
+gigabit Ethernet cards based on Intel's 82580 NIC. Because EEPROMs normally do not announce their size nor allow
+themselves to be identified, the controller relies on correct size values written to predefined addresses within the chip.
+**Flashrom** follows this scheme but assumes the minimum size of 16 kB (128 kb) if an unprogrammed EEPROM/card is detected.
+Intel specifies following EEPROMs to be compatible:
+Atmel AT25128, AT25256, Micron (ST) M95128, M95256 and OnSemi (Catalyst) CAT25CS128.
+
+
+ft2232_spi programmer
+^^^^^^^^^^^^^^^^^^^^^
+
+This module supports various programmers based on FTDI FT2232/FT4232H/FT232H chips including the DLP Design DLP-USB1232H,
+openbiosprog-spi, Amontec JTAGkey/JTAGkey-tiny/JTAGkey-2, Dangerous Prototypes Bus Blaster, Olimex ARM-USB-TINY/-H,
+Olimex ARM-USB-OCD/-H, OpenMoko Neo1973 Debug board (V2+), TIAO/DIYGADGET USB Multi-Protocol Adapter (TUMPA), TUMPA Lite,
+GOEPEL PicoTAP, Google Servo v1/v2, Tin Can Tools Flyswatter/Flyswatter 2 and Kristech KT-LINK.
+
+An optional parameter specifies the controller type, channel/interface/port it should support. For that you have to use the::
+
+ flashrom \-p ft2232_spi:type=model,port=interface
+
+syntax where ``model`` can be ``2232H``, ``4232H``, ``232H``, ``jtagkey``, ``busblaster``, ``openmoko``, ``arm-usb-tiny``,
+``arm-usb-tiny-h``, ``arm-usb-ocd``, ``arm-usb-ocd-h``, ``tumpa``, ``tumpalite``, ``picotap``, ``google-servo,
+``google-servo-v2``, ``google-servo-v2-legacy`` or ``kt-link``.
+``interface`` can be ``A``, ``B``, ``C``, or ``D``. The default model is ``4232H``, the default interface is ``A`` and
+GPIO is not used by default.
+
+If there is more than one ft2232_spi-compatible device connected, you can select which one should be used by specifying
+its serial number with the::
+
+ flashrom -p ft2232_spi:serial=number
+
+syntax where ``number`` is the serial number of the device (which can be found for example in the output of lsusb -v).
+
+All models supported by the **ft2232_spi** driver can configure the SPI clock rate by setting a divisor. The expressible
+divisors are all **even** numbers between 2 and 2^17 (=131072) resulting in SPI clock frequencies of 6 MHz down to about
+92 Hz for 12 MHz inputs (non-H chips) and 30 MHz down to about 458 Hz for 60 MHz inputs ('H' chips). The default divisor
+is set to 2, but you can use another one by specifying the optional ``divisor`` parameter with the::
+
+ flashrom -p ft2232_spi:divisor=div
+
+syntax. Using the parameter ``csgpiol`` (DEPRECATED - use ``gpiol`` instead) an additional CS# pin can be chosen,
+where the value can be a number between 0 and 3, denoting GPIOL0-GPIOL3 correspondingly. Example::
+
+ flashrom -p ft2232_spi:csgpiol=3
+
+The parameter ``gpiolX=[HLC]`` allows use of the GPIOL pins either as generic gpios with a fixed value during flashing
+or as additional CS# signal, where ``X`` can be a number between 0 and 3, denoting GPIOL0-GPIOL3 correspondingly.
+The parameter may be specified multiple times, one time per GPIOL pin. Valid values are ``H``, ``L`` and ``C``:
+
+* ``H`` - Set GPIOL output high
+* ``L`` - Set GPIOL output low
+* ``C`` - Use GPIOL as additional CS# output
+
+Example::
+
+ flashrom -p ft2232_spi:gpiol0=H
+
+**Note** that not all GPIOL pins are freely usable with all programmers as some have special functionality.
+
+
+serprog programmer
+^^^^^^^^^^^^^^^^^^
+
+This module supports all programmers speaking the serprog protocol. This includes some Arduino-based devices as well as
+various programmers by Urja Rannikko, Juhana Helovuo, Stefan Tauner, Chi Zhang and many others.
+
+A mandatory parameter specifies either a serial device (and baud rate) or an IP/port combination for communicating with
+the programmer. The device/baud combination has to start with ``dev=`` and separate the optional baud rate with a colon.
+For example::
+
+ flashrom -p serprog:dev=/dev/ttyS0:115200
+
+If no baud rate is given the default values by the operating system/hardware will be used.
+For IP connections you have to use the::
+
+ flashrom -p serprog:ip=ipaddr:port
+
+syntax. In case the device supports it, you can set the SPI clock frequency with the optional ``spispeed`` parameter.
+The frequency is parsed as hertz, unless an ``M``, or ``k`` suffix is given, then megahertz or kilohertz are used respectively.
+Example that sets the frequency to 2 MHz::
+
+ flashrom -p serprog:dev=/dev/device:baud,spispeed=2M
+
+More information about serprog is available in **serprog-protocol.txt** in the source distribution.
+
+
+buspirate_spi programmer
+^^^^^^^^^^^^^^^^^^^^^^^^
+
+A required ``dev`` parameter specifies the Bus Pirate device node and an optional ``spispeed`` parameter specifies the
+frequency of the SPI bus. The parameter delimiter is a comma. Syntax is::
+
+ flashrom -p buspirate_spi:dev=/dev/device,spispeed=frequency
+
+where ``frequency`` can be ``30k``, ``125k``, ``250k``, ``1M``, ``2M``, ``2.6M``, ``4M`` or ``8M`` (in Hz).
+The default is the maximum frequency of 8 MHz.
+
+The baud rate for communication between the host and the Bus Pirate can be specified with the optional ``serialspeed``
+parameter. Syntax is::
+
+ flashrom -p buspirate_spi:serialspeed=baud
+
+where ``baud`` can be ``115200``, ``230400``, ``250000`` or ``2000000`` (``2M``).
+The default is ``2M`` baud for Bus Pirate hardware version 3.0 and greater, and 115200 otherwise.
+
+An optional pullups parameter specifies the use of the Bus Pirate internal pull-up resistors. This may be needed if you
+are working with a flash ROM chip that you have physically removed from the board. Syntax is::
+
+ flashrom -p buspirate_spi:pullups=state
+
+where ``state`` can be ``on`` or ``off``.
+More information about the Bus Pirate pull-up resistors and their purpose is available
+`in a guide by dangerousprototypes <http://dangerousprototypes.com/docs/Practical_guide_to_Bus_Pirate_pull-up_resistors>`_.
+
+The state of the Bus Pirate power supply pins is controllable through an optional ``psus`` parameter. Syntax is::
+
+ flashrom -p buspirate_spi:psus=state
+
+where ``state`` can be ``on`` or ``off``.
+This allows the bus pirate to power the ROM chip directly. This may also be used to provide the required pullup voltage
+(when using the **pullups** option), by connecting the Bus Pirate's Vpu input to the appropriate Vcc pin.
+
+An optional aux parameter specifies the state of the Bus Pirate auxiliary pin.
+This may be used to drive the auxiliary pin high or low before a transfer.
+Syntax is::
+
+ flashrom -p buspirate_spi:aux=state
+
+where ``state`` can be ``high`` or ``low``. The default ``state`` is ``high``.
+
+
+pickit2_spi programmer
+^^^^^^^^^^^^^^^^^^^^^^
+
+An optional ``voltage`` parameter specifies the voltage the PICkit2 should use. The default unit is Volt if no unit is specified.
+You can use ``mV``, ``millivolt``, ``V`` or ``Volt`` as unit specifier. Syntax is::
+
+ flashrom \-p pickit2_spi:voltage=value
+
+where ``value`` can be ``0V``, ``1.8V``, ``2.5V``, ``3.5V`` or the equivalent in mV.
+
+An optional ``spispeed`` parameter specifies the frequency of the SPI bus. Syntax is::
+
+ flashrom -p pickit2_spi:spispeed=frequency
+
+where ``frequency`` can be ``250k``, ``333k``, ``500k`` or ``1M`` (in Hz). The default is a frequency of 1 MHz.
+
+
+dediprog programmer
+^^^^^^^^^^^^^^^^^^^
+
+An optional ``voltage`` parameter specifies the voltage the Dediprog should use. The default unit is Volt if no unit is specified.
+You can use ``mV``, ``milliVolt``, ``V`` or ``Volt`` as unit specifier. Syntax is::
+
+ flashrom -p dediprog:voltage=value
+
+where ``value`` can be ``0V``, ``1.8V``, ``2.5V``, ``3.5V`` or the equivalent in mV.
+
+An optional ``device`` parameter specifies which of multiple connected Dediprog devices should be used.
+Please be aware that the order depends on libusb's usb_get_busses() function and that the numbering starts at 0.
+Usage example to select the second device::
+
+ flashrom -p dediprog:device=1
+
+An optional ``spispeed`` parameter specifies the frequency of the SPI bus. The firmware on the device needs to be 5.0.0 or newer.
+Syntax is::
+
+ flashrom -p dediprog:spispeed=frequency
+
+where ``frequency`` can be ``375k``, ``750k``, ``1.5M``, ``2.18M``, ``3M``, ``8M``, ``12M`` or ``24M`` (in Hz).
+The default is a frequency of 12 MHz.
+
+An optional ``target`` parameter specifies which target chip should be used. Syntax is::
+
+ flashrom -p dediprog:target=value
+
+where ``value`` can be ``1`` or ``2`` to select target chip 1 or 2 respectively. The default is target chip 1.
+
+
+rayer_spi programmer
+^^^^^^^^^^^^^^^^^^^^
+
+The default I/O base address used for the parallel port is 0x378 and you can use the optional ``iobase`` parameter to
+specify an alternate base I/O address with the::
+
+ flashrom -p rayer_spi:iobase=baseaddr
+
+syntax where ``baseaddr`` is base I/O port address of the parallel port, which must be a multiple of four.
+Make sure to not forget the "0x" prefix for hexadecimal port addresses.
+
+The default cable type is the RayeR cable. You can use the optional ``type`` parameter to specify the cable type with the::
+
+ flashrom -p rayer_spi:type=model
+
+syntax where ``model`` can be ``rayer`` for the RayeR cable, ``byteblastermv`` for the Altera ByteBlasterMV,
+``stk200`` for the Atmel, ``STK200/300``, ``wiggler`` for the Macraigor Wiggler, ``xilinx`` for the Xilinx Parallel Cable III (DLC 5),
+or ``spi_tt`` for SPI Tiny Tools-compatible hardware.
+
+More information about the RayeR hardware is available at `RayeR's website <http://rayer.g6.cz/elektro/spipgm.htm>`_.
+The Altera ByteBlasterMV datasheet can be obtained from `Altera <http://www.altera.co.jp/literature/ds/dsbytemv.pdf>`_.
+For more information about the Macraigor Wiggler see `their company homepage <http://www.macraigor.com/wiggler.htm>`_.
+The schematic of the Xilinx DLC 5 was published in `a Xilinx guide <http://www.xilinx.com/support/documentation/user_guides/xtp029.pdf>`_.
+
+
+raiden_debug_spi programmer
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The target of the SPI flashing mux must be specified with the ``target`` parameter with the::
+
+ flashrom -p raiden_debug_spi:target=chip
+
+syntax, where ``chip`` is either the ``ap`` or ``ec`` to flash, otherwise a unspecified target terminates at the end-point.
+
+The default is to use the first available servo. You can use the optional ``serial`` parameter to specify the servo
+USB device serial number to use specifically with::
+
+ flashrom -p raiden_debug_spi:serial=XXX
+
+The servo device serial number can be found via ``lsusb``.
+Raiden will poll the ``ap`` target waiting for the system power to settle on the AP and EC flash devices.
+
+The optional ``custom_rst=true`` parameter changes the timeout value from 3ms to 10ms::
+
+ flashrom -p raiden_debug_spi:custom_rst=<true|false>
+
+syntax, where ``custom_rst=false`` is the implicit default timeout of 3ms. More information about the ChromiumOS servo
+hardware is available at `servos website <https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/HEAD/docs/servo_v4.md>`_.
+
+
+pony_spi programmer
+^^^^^^^^^^^^^^^^^^^
+
+The serial port (like /dev/ttyS0, /dev/ttyUSB0 on Linux or COM3 on windows) is specified using the mandatory ``dev``
+parameter. The adapter type is selectable between SI-Prog (used for SPI devices with PonyProg 2000) or a custom made
+serial bitbanging programmer named "serbang". The optional ``type`` parameter accepts the values ``si_prog`` (default)
+or ``serbang``.
+
+Information about the SI-Prog adapter can be found at `its website <http://www.lancos.com/siprogsch.html>`_.
+
+An example call to **flashrom** is::
+
+ flashrom -p pony_spi:dev=/dev/ttyS0,type=serbang
+
+Please note that while USB-to-serial adapters work under certain circumstances, this slows down operation considerably.
+
+
+ogp_spi programmer
+^^^^^^^^^^^^^^^^^^
+
+The flash ROM chip to access must be specified with the ``rom`` parameter::
+
+ flashrom -p ogp_spi:rom=name
+
+Where ``name`` is either ``cprom`` or ``s3`` for the configuration ROM and ``bprom`` or ``bios`` for the BIOS ROM.
+If more than one card supported by the **ogp_spi** programmer is installed in your system, you have to specify the PCI
+address of the card you want to use with the ``pci=`` parameter as explained in the **nic3com** et al. section above.
+
+
+linux_mtd programmer
+^^^^^^^^^^^^^^^^^^^^
+
+You may specify the MTD device to use with the::
+
+ flashrom -p linux_mtd:dev=/dev/mtdX
+
+syntax where ``/dev/mtdX`` is the Linux device node for your MTD device. If left unspecified the first MTD device found
+(e.g. /dev/mtd0) will be used by default.
+
+Please note that the linux_mtd driver only works on Linux.
+
+
+linux_spi programmer
+^^^^^^^^^^^^^^^^^^^^
+
+You have to specify the SPI controller to use with the::
+
+ flashrom -p linux_spi:dev=/dev/spidevX.Y
+
+syntax where ``/dev/spidevX.Y`` is the Linux device node for your SPI controller.
+
+In case the device supports it, you can set the SPI clock frequency with the optional ``spispeed`` parameter.
+The frequency is parsed as kilohertz. Example that sets the frequency to 8 MHz::
+
+ flashrom -p linux_spi:dev=/dev/spidevX.Y,spispeed=8000
+
+Please note that the linux_spi driver only works on Linux.
+
+
+mstarddc_spi programmer
+^^^^^^^^^^^^^^^^^^^^^^^
+
+The Display Data Channel (DDC) is an I2C bus present on VGA and DVI connectors, that allows exchanging information
+between a computer and attached displays. Its most common uses are getting display capabilities through EDID
+(at I2C address 0x50) and sending commands to the display using the DDC/CI protocol (at address 0x37).
+On displays driven by MSTAR SoCs, it is also possible to access the SoC firmware flash (connected to the Soc through another SPI bus)
+using an In-System Programming (ISP) port, usually at address 0x49. This **flashrom** module allows the latter via Linux's I2C driver.
+
+**IMPORTANT:**
+Before using this programmer, the display **MUST** be in standby mode, and only connected to the computer that will run
+**flashrom** using a VGA cable, to an inactive VGA output. It absolutely **MUST NOT** be used as a display during the procedure!
+
+You have to specify the DDC/I2C controller and I2C address to use with the::
+
+ flashrom -p mstarddc_spi:dev=/dev/i2c-X:YY
+
+syntax where ``/dev/i2c-X`` is the Linux device node for your I2C controller connected to the display's DDC channel, and
+``YY`` is the (hexadecimal) address of the MSTAR ISP port (address 0x49 is usually used).
+Example that uses I2C controller /dev/i2c-1 and address 0x49::
+
+ flashrom -p mstarddc_spi:dev=/dev/i2c-1:49
+
+It is also possible to inhibit the reset command that is normally sent to the display once the **flashrom** operation is
+completed using the optional ``noreset`` parameter. A value of 1 prevents **flashrom** from sending the reset command.
+Example that does not reset the display at the end of the operation::
+
+ flashrom -p mstarddc_spi:dev=/dev/i2c-1:49,noreset=1
+
+Please note that sending the reset command is also inhibited if an error occurred during the operation.
+To send the reset command afterwards, you can simply run **flashrom** once more, in chip probe mode (not specifying an operation),
+without the ``noreset`` parameter, once the flash read/write operation you intended to perform has completed successfully.
+
+Please also note that the mstarddc_spi driver only works on Linux.
+
+
+ch341a_spi programmer
+^^^^^^^^^^^^^^^^^^^^^
+
+The WCH CH341A programmer does not support any parameters currently. SPI frequency is fixed at 2 MHz, and CS0 is used
+as per the device.
+
+
+ch347_spi programmer
+^^^^^^^^^^^^^^^^^^^^
+
+The WCH CH347 programmer does not currently support any parameters. SPI frequency is fixed at 2 MHz, and CS0 is used
+as per the device.
+
+ni845x_spi programmer
+^^^^^^^^^^^^^^^^^^^^^
+
+An optional ``voltage`` parameter could be used to specify the IO voltage. This parameter is available for the NI USB-8452 device.
+The default unit is Volt if no unit is specified. You can use ``mV``, ``milliVolt``, ``V`` or ``Volt`` as unit specifier.
+Syntax is::
+
+ flashrom -p ni845x_spi:voltage=value
+
+where ``value`` can be ``1.2V``, ``1.5V``, ``1.8V``, ``2.5V``, ``3.3V`` or the equivalent in mV.
+
+In the case if none of the programmer's supported IO voltage is within the supported voltage range of the detected flash
+chip the **flashrom** will abort the operation (to prevent damaging the flash chip).
+You can override this behaviour by passing ``yes`` to the ``ignore_io_voltage_limits`` parameter
+(for e.g. if you are using an external voltage translator circuit). Syntax is::
+
+ flashrom -p ni845x_spi:ignore_io_voltage_limits=yes
+
+You can use the ``serial`` parameter to explicitly specify which connected NI USB-845x device should be used. You should
+use your device's 7 digit hexadecimal serial number. Usage example to select the device with 1230A12 serial number::
+
+ flashrom -p ni845x_spi:serial=1230A12
+
+An optional ``spispeed`` parameter specifies the frequency of the SPI bus. Syntax is::
+
+ flashrom -p ni845x_spi:spispeed=frequency
+
+where ``frequency`` should a number corresponding to the desired frequency in kHz.
+The maximum ``frequency`` is 12 MHz (12000 kHz) for the USB-8451 and 50 MHz (50000 kHz) for the USB-8452.
+The default is a frequency of 1 MHz (1000 kHz).
+
+An optional ``cs`` parameter specifies which target chip select line should be used. Syntax is::
+
+ flashrom -p ni845x_spi:csnumber=value
+
+where ``value`` should be between ``0`` and ``7``. By default the CS0 is used.
+
+
+digilent_spi programmer
+^^^^^^^^^^^^^^^^^^^^^^^
+
+An optional ``spispeed`` parameter specifies the frequency of the SPI bus. Syntax is::
+
+ flashrom -p digilent_spi:spispeed=frequency
+
+where ``frequency`` can be ``62.5k``, ``125k``, ``250k``, ``500k``, ``1M``, ``2M`` or ``4M`` (in Hz).
+The default is a frequency of 4 MHz.
+
+
+dirtyjtag_spi programmer
+^^^^^^^^^^^^^^^^^^^^^^^^
+
+An optional ``freq`` parameter specifies the frequency of the SPI bus. Syntax is::
+
+ flashrom -p dirtyjtag_spi:spispeed=frequency
+
+where ``spispeed`` can be any value in hertz, kilohertz or megahertz supported by the programmer.
+The default is a frequency of 100 KHz.
+
+
+jlink_spi programmer
+^^^^^^^^^^^^^^^^^^^^
+
+This module supports SEGGER J-Link and compatible devices.
+
+The **MOSI** signal of the flash chip must be attached to **TDI** pin of the programmer, **MISO** to **TDO** and
+**SCK** to **TCK**. The chip select (**CS**) signal of the flash chip can be attached to different pins of the
+programmer which can be selected with the::
+
+ flashrom -p jlink_spi:cs=pin
+
+syntax where ``pin`` can be either ``TRST``, ``RESET`` or ``TMS``. The default pin for chip select is ``RESET``.
+Note that, when using ``RESET``, it is normal that the indicator LED blinks orange or red.
+
+Additionally, the ``Tref`` pin of the programmer must be attached to the logic level of the flash chip.
+The programmer measures the voltage on this pin and generates the reference
+voltage for its input comparators and adapts its output voltages to it.
+
+Pinout for devices with 20-pin JTAG connector::
+
+ +-------+
+ | 1 2 | 1: VTref 2:
+ | 3 4 | 3: TRST 4: GND
+ | 5 6 | 5: TDI 6: GND
+ +-+ 7 8 | 7: TMS 8: GND
+ | 9 10 | 9: TCK 10: GND
+ | 11 12 | 11: 12: GND
+ +-+ 13 14 | 13: TDO 14:
+ | 15 16 | 15: RESET 16:
+ | 17 18 | 17: 18:
+ | 19 20 | 19: PWR_5V 20:
+ +-------+
+
+If there is more than one compatible device connected, you can select which one should be used by specifying its serial
+number with the::
+
+ flashrom -p jlink_spi:serial=number
+
+syntax where ``number`` is the serial number of the device (which can be found for example in the output of ``lsusb -v``).
+
+The SPI speed can be selected by using the::
+
+ flashrom -p jlink_spi:spispeed=frequency
+
+syntax where ``frequency`` is the SPI clock frequency in kHz. The maximum speed depends on the device in use.
+
+The ``power=on`` option can be used to activate the 5 V power supply (PWR_5V) of the J-Link during a flash operation.
+
+
+stlinkv3_spi programmer
+^^^^^^^^^^^^^^^^^^^^^^^
+
+This module supports SPI flash programming through the STMicroelectronics STLINK V3 programmer/debugger's SPI bridge interface::
+
+ flashrom -p stlinkv3_spi
+
+If there is more than one compatible device connected, you can select which one should be used by specifying its
+serial number with the::
+
+ flashrom -p stlinkv3_spi:serial=number
+
+syntax where ``number`` is the serial number of the device (which can be found for example in the output of ``lsusb -v``).
+
+The SPI speed can be selected by using the::
+
+ flashrom -p stlinkv3_spi:spispeed=frequency
+
+syntax where ``frequency`` is the SPI clock frequency in kHz. If the passed frequency is not supported by the adapter
+the nearest lower supported frequency will be used.
+
+
+realtek_mst_i2c_spi, parade_lspcon and mediatek_i2c_spi programmers
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+These programmers tunnel SPI commands through I2C-connected devices. The I2C bus over which communication occurs must be
+specified either by device path with the ``devpath`` option::
+
+ flashrom -p realtek_mst_i2c_spi:devpath=/dev/i2c-8
+
+or by a bus number with the ``bus`` option, which implies a device path like ``/dev/i2c-N`` where ``N`` is the specified
+bus number::
+
+ flashrom -p parade_lspcon:bus=8
+
+
+realtek_mst_i2c_spi programmer
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+This programmer supports SPI flash programming for chips attached to Realtek DisplayPort MST hubs, themselves accessed
+through I2C (tunneling SPI flash commands through the MST hub's I2C connection with the host).
+
+
+In-system programming (ISP) mode
+""""""""""""""""""""""""""""""""
+
+The ``reset_mcu`` and ``enter_isp`` options provide control over device mode changes, where each can be set to ``0``
+or ``1`` to enable or disable the corresponding mode transition.
+
+``enter_isp`` defaults to ``1``, and if enabled will issue commands to the MST hub when beginning operation to put it
+into ISP mode.
+
+``reset_mcu`` defaults to ``0``, and if enabled will issue a reset command to the MST hub on programming completion,
+causing it to exit ISP mode and to reload its own firmware from flash.
+
+``allow_brick`` defaults to ``no``, however must be set explicitly to ``yes`` to allow the driver to run if you are sure
+you have a MST chip.
+
+The hub must be in ISP mode for SPI flash access to be possible, so it is usually only useful to disable ``enter_isp``
+if an earlier invocation avoided resetting it on completion. For instance, to erase the flash and rewrite it with the
+contents of a file without resetting in between (which could render it nonfunctional if attempting to load firmware
+from a blank flash)::
+
+ flashrom -p realtek_mst_i2c_spi:bus=0,enter_isp=1,reset_mcu=0 -E
+
+ flashrom -p realtek_mst_i2c_spi:bus=0,enter_isp=0,reset_mcu=1 -w new.bin
+
+
+parade_lspcon programmer
+^^^^^^^^^^^^^^^^^^^^^^^^
+
+This programmer supports SPI flash programming for chips attached to Parade Technologies DisplayPort-to-HDMI level
+shifter/protocol converters (LSPCONs), e.g. the PS175. Communication to the SPI flash is tunneled through the LSPCON
+over I2C.
+
+
+mediatek_i2c_spi programmer
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+This programmer supports SPI flash programming for chips attached to some Mediatek display controllers, themselves
+accessed through I2C (tunneling SPI flash commands through an I2C connection with the host).
+
+The programmer is designed to support the TSUMOP82JUQ integrated display driver and scaler as used in the Google Meet
+Series One Desk 27 (which runs a version of ChromeOS and uses **flashrom** in its ``tsum-scaler-updater`` scripts that ship
+with the OS). Other chips may use compatible protocols but have not been tested with this programmer, and external chip
+IOs may need to be controlled through other non- **flashrom** means to configure the chip in order for it to operate as expected.
+
+``devpath`` and ``bus`` options select the I2C bus to use, as described previously. ``allow_brick`` defaults to ``no``,
+and must explicitly be set to ``yes`` in order for the programmer to operate. This is required because there is no
+mechanism in the driver to positively identify that a given I2C bus is actually connected to a supported device.
+
+
+EXAMPLES
+--------
+
+To back up and update your BIOS, run::
+
+ flashrom -p internal -r backup.rom -o backuplog.txt
+ flashrom -p internal -w newbios.rom -o writelog.txt
+
+Please make sure to copy backup.rom to some external media before you try to write. That makes offline recovery easier.
+
+If writing fails and **flashrom** complains about the chip being in an unknown state, you can try to restore the backup by running::
+
+ flashrom -p internal -w backup.rom -o restorelog.txt
+
+If you encounter any problems, please contact us and supply backuplog.txt, writelog.txt and restorelog.txt.
+See section **BUGS** for contact info.
+
+
+EXIT STATUS
+-----------
+
+**flashrom** exits with 0 on success, 1 on most failures but with 3 if a call to mmap() fails.
+
+
+REQUIREMENTS
+------------
+
+**flashrom** needs different access permissions for different programmers.
+
+* internal
+
+ * needs raw memory access
+ * PCI configuration space access
+ * raw I/O port access (x86)
+ * MSR access (x86)
+
+* atavia
+
+ * needs PCI configuration space access
+
+* nic3com, nicrealtek, nicnatsemi
+
+ * need PCI configuration space read access
+ * raw I/O port access
+
+* atahpt
+
+ * needs PCI configuration space access
+ * raw I/O port access
+
+* gfxnvidia, drkaiser, it8212
+
+ * need PCI configuration space access
+ * raw memory access
+
+* rayer_spi
+
+ * needs raw I/O port access
+
+* raiden_debug_spi
+
+ * needs access to the respective USB device via libusb API version 1.0
+
+* satasii, nicintel, nicintel_eeprom, nicintel_spi
+
+ * need PCI configuration space read access
+ * raw memory access
+
+* satamv, atapromise
+
+ * need PCI configuration space read access
+ * raw I/O port access
+ * raw memory access
+
+* serprog
+
+ * needs TCP access to the network or userspace access to a serial port
+
+* buspirate_spi
+
+ * needs userspace access to a serial port
+
+* ft2232_spi, usbblaster_spi, pickit2_spi
+
+ * need access to the respective USB device via libusb API version 1.0
+
+* ch341a_spi, dediprog
+
+ * need access to the respective USB device via libusb API version 1.0
+
+* dummy
+
+ * needs no access permissions at all
+
+* internal, nic3com, nicrealtek, nicnatsemi, gfxnvidia, drkaiser, satasii, satamv, atahpt, atavia, atapromise, asm106x
+
+ * have to be run as superuser/root
+ * need raw access permission
+
+* serprog, buspirate_spi, dediprog, usbblaster_spi, ft2232_spi, pickit2_spi, ch341a_spi, digilent_spi, dirtyjtag_spi
+
+ * can be run as normal user on most operating systems if appropriate device permissions are set
+
+* ogp
+
+ * needs PCI configuration space read access and raw memory access
+
+* realtek_mst_i2c_spi, parade_lspcon
+
+ * need userspace access to the selected I2C bus
+
+On OpenBSD, you can obtain raw access permission by setting::
+
+ securelevel=-1
+
+in **/etc/rc.securelevel** and rebooting, or rebooting into single user mode.
+
+
+BUGS
+----
+
+You can report bugs, ask us questions or send success reports via our communication channels listed here:
+`Contact <https://www.flashrom.org/Contact>`_
+
+Also, we provide a `pastebin service <https://paste.flashrom.org>`_ that is very useful to share logs without spamming
+the communication channels.
+
+
+Laptops
+-------
+
+Using **flashrom** on older laptops is dangerous and may easily make your hardware unusable. **flashrom** will attempt to detect
+if it is running on a susceptible laptop and restrict flash-chip probing for safety reasons. Please see the detailed
+discussion of this topic and associated **flashrom** options in the **Laptops** paragraph in the **internal programmer**
+subsection of the **PROGRAMMER-SPECIFIC INFORMATION** section and the information `in our wiki <https://flashrom.org/Laptops>`_.
+
+One-time programmable (OTP) memory and unique IDs
+
+Some flash chips contain OTP memory often denoted as **security registers**. They usually have a capacity in the range
+of some bytes to a few hundred bytes and can be used to give devices unique IDs etc. **flashrom** is not able to read
+or write these memories and may therefore not be able to duplicate a chip completely. For chip types known to include
+OTP memories a warning is printed when they are detected.
+
+Similar to OTP memories are unique, factory programmed, unforgeable IDs. They are not modifiable by the user at all.
+
+
+LICENSE
+-------
+
+**flashrom** is covered by the GNU General Public License (GPL), version 2. Some files are additionally available
+under any later version of the GPL.
+
+
+COPYRIGHT
+---------
+Please see the individual files.
+
+
+AUTHORS
+-------
+
+Andrew Morgan, Anastasia Klimchuk, Carl-Daniel Hailfinger, Claus Gindhart, David Borg, David Hendricks, Dominik Geyer,
+Edward O'Callaghan, Eric Biederman, Giampiero Giancipoli, Helge Wagner, Idwer Vollering, Joe Bao, Joerg Fischer,
+Joshua Roys, Kyösti Mälkki, Luc Verhaegen, Li-Ta Lo, Mark Marshall, Markus Boas, Mattias Mattsson, Michael Karcher,
+Nikolay Petukhov, Patrick Georgi, Peter Lemenkov, Peter Stuge, Reinder E.N. de Haan, Ronald G. Minnich, Ronald Hoogenboom,
+Sean Nelson, Stefan Reinauer, Stefan Tauner, Stefan Wildemann, Stephan Guilloux, Steven James, Urja Rannikko, Uwe Hermann,
+Wang Qingpei, Yinghai Lu and others, please see the **flashrom** git history for details.
+
+All still active authors can be reached via `the mailing list <flashrom\@flashrom.org>`_.
+
+This manual page was written by `Uwe Hermann <uwe\@hermann-uwe.de>`_, Carl-Daniel Hailfinger, Stefan Tauner and others.
+It is licensed under the terms of the GNU GPL (version 2 or later).
diff --git a/doc/conf.py b/doc/conf.py
new file mode 100644
index 000000000..be9cc0174
--- /dev/null
+++ b/doc/conf.py
@@ -0,0 +1,49 @@
+# Configuration file for the Sphinx documentation builder.
+#
+# For the full list of built-in configuration values, see the documentation:
+# https://www.sphinx-doc.org/en/master/usage/configuration.html
+
+import os
+
+# -- Project information -----------------------------------------------------
+# https://www.sphinx-doc.org/en/master/usage/configuration.html#project-information
+
+project = 'flashrom'
+# copyright = '2023, The flashrom authors'
+author = 'The flashrom authors'
+
+# -- General configuration ---------------------------------------------------
+# https://www.sphinx-doc.org/en/master/usage/configuration.html#general-configuration
+
+master_doc = 'index' # this is needed for old versions
+
+extensions = [
+ 'sphinx.ext.todo'
+]
+
+#templates_path = ['_templates']
+exclude_patterns = []
+
+# -- Options for Todo extension ----------------------------------------------
+# https://www.sphinx-doc.org/en/master/usage/extensions/todo.html
+
+# If this is True, todo and todolist produce output, else they produce nothing. The default is False.
+todo_include_todos = False
+
+
+
+# -- Options for HTML output -------------------------------------------------
+# https://www.sphinx-doc.org/en/master/usage/configuration.html#options-for-html-output
+
+html_theme = 'alabaster'
+#html_static_path = ['_static']
+
+html_favicon = 'logo/flashrom_icon_color-32x32.ico'
+
+
+# -- Options for manual page output --------------------------------------------
+man_make_section_directory = True
+man_show_urls = True
+man_pages = [
+ ('classic_cli_manpage', project, '', [], 8),
+]
diff --git a/doc/contact.rst b/doc/contact.rst
new file mode 100644
index 000000000..5bcac3fd0
--- /dev/null
+++ b/doc/contact.rst
@@ -0,0 +1,157 @@
+Contact
+========
+.. The extra = is needed to prevent git from throwing a `leftover conflict marker`
+ error when commiting.
+
+.. _mailing list:
+
+Mailing List
+------------
+Flashrom related mails are welcome on the flashrom mailing list at `flashrom@flashrom.org <mailto:flashrom@flashrom.org>`_.
+Please do NOT send any BIOS images or F segment dumps to the list!
+
+E-mails with binary files attached will be rejected. Images for things such as scope or logic analyzer traces are acceptable
+if hosted on a third-party photo sharing service that assigns a unique URL to the image, such as Google Photos.
+This prevents the photo URL from being abused for malicious or inappropriate content.
+
+Please note that the list is moderated for non-subscribers and we recommend to subscribe first.
+
+Subscription
+""""""""""""
+https://mail.coreboot.org/postorius/lists/flashrom.flashrom.org/
+
+Archives
+""""""""
+| https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/
+| https://mail.coreboot.org/pipermail/flashrom/ (Up to Dec. 2018)
+| https://marc.info/?l=flashrom
+| https://www.mail-archive.com/flashrom@flashrom.org/
+
+Moderation rules
+""""""""""""""""
+If your mail is too big (the current limit is 256 kB) or if you're not on the subscriber list, your mail will be held for moderation.
+If your mail contains any BIOS images or F segment dumps (instead of links which are fine), the mail will be rejected for legal reasons
+(we do not have the right to distribute BIOS images).
+
+Real time chats
+---------------
+
+Flashrom has real time channels where you have the chance to talk to people being involved or interested in the project.
+Most of the discussion is about flashrom development, contributions, tech talk and user help.
+
+You are welcome to join and discuss current and future flashrom development, ideas and contributions.
+
+If you have a problem and would like to get help, don't ask for help. Instead, just **explain** your problem right away,
+and make sure to **describe** the situation as much as possible, so that other people can understand you and provide meaningful answers.
+Otherwise, others have to ask or guess the details of your problem, which is frustrating for both parties.
+
+Should you need to paste lots of text (more than three lines), please use a `paste service <https://en.wikipedia.org/wiki/Pastebin>`_.
+For flashrom logs, feel free to use `paste.flashrom.org <https://paste.flashrom.org>`_.
+Other good paste services are `ix.io <http://ix.io/>`_, `paste.rs <https://paste.rs/>`_, `bpaste.net <https://bpaste.net/>`_,
+`gist.github.com <https://gist.github.com/>`_ and `dpaste.com <http://dpaste.com/>`_.
+
+Questions on `coreboot <https://coreboot.org>`_, `OpenBIOS <http://www.openbios.info/>`_, firmware and related topics are welcome in **#coreboot** on the same server.
+
+IRC
+"""
+
+You can join `#flashrom <irc://irc.libera.chat/#flashrom>`_
+channel on the `Libera.chat <https://www.libera.chat/>`_ `IRC <https://en.wikipedia.org/wiki/Internet_Relay_Chat>`_ network.
+If you don't have an IRC client, you can use the Libera.chat `webchat <https://web.libera.chat/#flashrom>`_.
+
+**#flashrom** channel is bridged to `Matrix <https://matrix.org/>`_.
+If you would like to join, you can use `this invite link <https://matrix.to/#/#flashrom:libera.chat>`_.
+
+Do note that IRC's nature has a significant effect on conversations. People from all over the world can join this channel
+with many different cultures and timezones. Most people are in the `CET timezone <https://en.wikipedia.org/wiki/Central_European_Time>`_,
+so the channel may be very quiet during `CET nighttime <https://time.is/CET>`_.
+
+If you receive no replies, **please be patient**.
+After all, silence is better than getting replied with `"IDK" <https://en.wiktionary.org/wiki/IDK>`_.
+Frequently, somebody knows the answer, but hasn't checked IRC yet. In any case, please **do not leave the channel while waiting for an answer!**
+Since IRC does not store messages, replying to somebody who left the channel is **impossible**.
+
+To have persistence on IRC, you can set up an `IRC bouncer <https://en.wikipedia.org/wiki/Internet_Relay_Chat#Bouncer>`_
+like `ZNC <https://en.wikipedia.org/wiki/ZNC>`_, or use `IRCCloud <https://www.irccloud.com/>`_.
+Please **do not publish any logs** of this channel.
+
+Most of the time, people use IRC on wider-than-tall screens. Because of this, consider that pressing the return key is expensive.
+Instead of sending lots of tiny messages with only about two words, prefer using longer sentences, spaces and punctuation symbols.
+If reading and understanding your messages is easy, replying to them is also easy.
+
+Discord
+"""""""
+
+Flashrom Discord channel is hosted on coreboot's server. Once you join, you will be able to see all coreboot's and flashrom's channels in one place.
+To join, use the `invite link <https://discord.gg/dgcrkwVyeR>`_.
+
+Dev meeting
+-----------
+Flashrom developers community runs an online meeting every two weeks.
+The main purpose of the meeting is to discuss development plans, ideas,
+current ongoing projects, pending patches, and sometimes organisational questions.
+
+Note this meeting is NOT:
+
+* troubleshooting session
+* tech support forum
+* user training session
+
+For questions above, please use IRC or the mailing list.
+
+Time of meeting
+"""""""""""""""
+It runs once every two weeks.
+
+**IMPORTANT**: please calculate meeting time for your local timezone.
+
+Between November and March (inclusive)
+
+ **Wednesday 21:00-22:00 UTC+0**
+
+ also known as
+
+ | Wednesday 13.00-14.00 Pacific Standard Time UTC-8
+ | Wednesday 22.00-23.00 Central European Time UTC+1
+ | Thursday 8.00-9.00am Australian Eastern Daylight Time UTC+11
+
+Between April and September (inclusive)
+
+ **Thursday 6.00-7.00am UTC+0**
+
+ also known as
+
+ | Wednesday 11pm-midnight Pacific Daylight Time UTC-7
+ | Thursday 8.00-9.00am Central European Summer Time UTC+2
+ | Thursday 16.00-17.00 Australian Eastern Standard Time UTC+10
+
+The last week of March and 4 weeks of October there are no meetings
+This is because daylight saving time changes are happening on different dates in different locations, and setting up meeting time becomes too complicated.
+
+FAQ
+"""
+**When is the next meeting?**
+
+Look into the meeting notes `document <https://docs.google.com/document/d/18qKvEbfPszjsJJGJhwi8kRVDUG3GZkADzQSH6WFsKqw/edit?usp=sharing>`_.
+The top entry, on the first page, with the date in the future, and empty list of attendees - is the next meeting.
+
+
+**How to join the meeting?**
+
+In the meeting notes `document <https://docs.google.com/document/d/18qKvEbfPszjsJJGJhwi8kRVDUG3GZkADzQSH6WFsKqw/edit?usp=sharing>`_,
+on the top it says “to join, click the link”, click the link.
+
+
+**Do I need an invitation to join the meeting?**
+
+No, just join.
+
+
+**Do I need to create an account anywhere?**
+
+No, you can join without an account, and view/comment on the meeting doc without an account.
+
+
+**How do I add a topic to the agenda?**
+
+Add comments/suggestions on the meeting doc, and they will be accepted shortly after.
diff --git a/doc/dev_guide/building_from_source.rst b/doc/dev_guide/building_from_source.rst
new file mode 100644
index 000000000..64250dd09
--- /dev/null
+++ b/doc/dev_guide/building_from_source.rst
@@ -0,0 +1,288 @@
+Building from source
+====================
+
+You're going to need the following tools to get started:
+
+* gcc or clang
+* meson
+* ninja
+* pkg-config
+* sphinx-build*
+
+| \* optional, to build man-pages and html documentation
+
+And the following dependencies:
+
+* cmocka [#b1]_
+* linux-headers [#b2]_
+* libpci [#b2]_
+* libusb1 [#b2]_
+* libftdi1 [#b2]_
+* libjaylink [#b2]_
+* NI-845x driver & library package [#b3]_
+
+.. [#b1] | optional, for building unit testing
+.. [#b2] | optional, depending on the selected programmer
+.. [#b3] | optional, proprietary and Windows only. (See Windows build instructions)
+
+If you are cross compiling, install the dependencies for your target.
+
+TL;DR
+-----
+::
+
+ meson setup builddir
+ meson compile -C builddir
+ meson install -C builddir
+
+
+.. _installing-dependencies:
+
+Installing dependencies
+-----------------------
+
+.. todo:: Move the bullet points to `tabs <https://www.w3schools.com/howto/howto_js_tabs.asp>`_
+
+ * No external dependencies (documentation should be build without fetching all of pypi)
+ * No Javascript?
+
+* Linux
+ * Debian / Ubuntu
+ ::
+
+ apt-get install -y \
+ gcc meson ninja-build pkg-config python3-sphinx \
+ libcmocka-dev libpci-dev libusb-1.0-0-dev libftdi1-dev libjaylink-dev
+
+ * ArchLinux / Manjaro
+ ::
+
+ pacman -S --noconfirm \
+ gcc meson ninja pkg-config python-sphinx cmocka \
+ pciutils libusb libftdi libjaylink
+
+ * openSUSE / SUSE
+ ::
+
+ zypper install -y \
+ gcc meson ninja pkg-config python3-Sphinx \
+ libcmocka-devel pciutils-devel libusb-1_0-devel libftdi1-devel libjaylink-devel
+
+ * NixOS / nixpkgs
+ * There is a ``shell.nix`` under ``scripts/``
+
+ ::
+
+ nix-shell -p \
+ gcc meson ninja pkg-config sphinx \
+ cmocka pciutils libusb1 libftdi1 libjaylink
+
+ * Alpine Linux
+ ::
+
+ apk add \
+ build-base meson ninja pkgconf py3-sphinx \
+ cmocka-dev pciutils-dev libusb-dev libjaylink-dev
+
+* Windows
+ * MSYS2
+ Install `MSYS2 <https://www.msys2.org/>`_ and ensure it is `fully updated <https://www.msys2.org/docs/updating/>`_.
+
+ * ``libpci`` is not available through the package manager and pci based programmer are not supported on Windows.
+ * ``ni845x_spi`` is only available with the proprietary library from National Instruments. Download and install the driver
+ from `ni.com <https://www.ni.com/en-us/support/downloads/drivers/download.ni-845x-driver-software.html>`_ and build flashrom
+ for **32-bit**. Add ``-Dprogrammer=ni845x_spi`` to your meson configuration.
+
+ In the MINGW64 shell run::
+
+ pacman -Sy \
+ mingw-w64-x86_64-gcc mingw-w64-x86_64-meson mingw-w64-x86_64-ninja mingw-w64-x86_64-pkg-config mingw-w64-x86_64-python-sphinx \
+ mingw-w64-x86_64-cmocka mingw-w64-x86_64-libusb mingw-w64-x86_64-libftdi mingw-w64-x86_64-libjaylink-git
+
+ For building flashrom as 32-bit application, use the MSYS2 MINGW32 shell and run::
+
+ pacman -Sy \
+ mingw-w64-i686-gcc mingw-w64-i686-meson mingw-w64-i686-ninja mingw-w64-i686-pkg-config mingw-w64-i686-python-sphinx \
+ mingw-w64-i686-cmocka mingw-w64-i686-libusb mingw-w64-i686-libftdi mingw-w64-i686-libjaylink-git
+
+* MacOS
+ * Homebrew
+ * ``libpci`` is not available through the package manager
+ * ``libjaylink`` is not available through the package manager
+
+ ::
+
+ brew install \
+ meson ninja pkg-config sphinx-doc \
+ libusb libftdi
+
+* BSD
+ * FreeBSD / DragonFlyBSD
+ * ``libusb1`` is part of the system
+ * ``libjaylink`` is not available through the package manager
+
+ ::
+
+ pkg install \
+ meson ninja pkgconf py39-sphinx \
+ cmocka libpci libftdi1
+
+ * OpenBSD
+ * ``libjaylink`` is not available through the package manager
+
+ ::
+
+ pkg_add \
+ meson ninja pkg-config py39-sphinx\
+ cmocka pciutils libusb1 libftdi1
+
+ * NetBSD
+ * ``libjaylink`` is not available through the package manager
+ * note: https://www.cambus.net/installing-ca-certificates-on-netbsd/
+
+ ::
+
+ pkgin install \
+ meson ninja pkg-config py39-sphinx \
+ cmocka pciutils libusb1 libftdi1
+
+* OpenIndiana (Illumos, Solaris, SunOS)
+ * ``libpci`` missing, pciutils is build without it
+ * ``libftdi1`` & ``libjaylink`` are not available through the package manager
+ * TODO: replace ``build-essential`` with the default compiler
+
+ ::
+
+ pkg install build-essential meson ninja cmocka libusb-1
+
+* DJGPP-DOS
+ * Get `DJGPP <https://www.delorie.com/djgpp/>`_
+ * A great build script can be found `here <https://github.com/andrewwutw/build-djgpp>`_
+ * Download the `pciutils <https://mj.ucw.cz/sw/pciutils/>`_ sources
+
+ | Run the following commands in the the pciutils directory to build libpci for DOS.
+ | Replace ``<DOS_INSTALL_ROOT>`` with your cross-compile install root.
+
+ ::
+
+ make install-lib \
+ ZLIB=no \
+ DNS=no \
+ HOST=i386-djgpp-djgpp \
+ CROSS_COMPILE=i586-pc-msdosdjgpp- \
+ STRIP="--strip-program=i586-pc-msdosdjgpp-strip -s" \
+ PREFIX=<DOS_INSTALL_ROOT>
+
+ Point pkg-config to the ``<DOS_INSTALL_ROOT>`` ::
+
+ export PKG_CONFIG_SYSROOT=<DOS_INSTALL_ROOT>
+
+ * To compile flashrom use the ``meson_cross/i586_djgpp_dos.txt`` cross-file
+ * You will need `CWSDPMI.EXE <https://sandmann.dotster.com/cwsdpmi/>`_ to run flashrom
+
+* libpayload
+ .. todo:: Add building instructions for libpayload
+
+
+Configuration
+-------------
+In the flashrom repository run::
+
+ meson setup [builtin options] [flashrom options] <builddir>
+
+Mesons ``[builtin options]`` can be displayed with ``meson setup --help``.
+The flashrom specific options can be found in ``meson_options.txt`` in the top-level
+directory of flashrom and are used like in cmake with ``-Doption=value``
+Run ``meson configure`` to display all configuration options.
+
+.. todo:: Write a sphinx extension to render ``meson_options.txt`` here
+
+
+Configuration for Crossbuilds
+-----------------------------
+Flashrom specific cross-files can be found in the ``meson_cross`` folder.
+To use them run::
+
+ meson setup --cross-file <path/to/crossfile> [builtin options] [flashrom options] <builddir>
+
+The options are the same as the normal configuration options. For more information see
+https://mesonbuild.com/Cross-compilation.html
+
+
+Compiling
+---------
+Run::
+
+ meson compile -C <builddir>
+
+
+Update configuration
+--------------------
+If you want to change your initial configuration for some reason
+(for example you discovered that a programmer is missing), run::
+
+ meson configure [updated builtin options] [updated flashrom options] <builddir>
+
+
+Unit Tests
+----------
+To execute the unit tests run::
+
+ meson test -C <builddir>
+
+You will get a summary of the unit test results at the end.
+
+
+Code coverage
+"""""""""""""
+gcov
+ Due to a bug in lcov, the html file will only be correct if lcov is not
+ installed and gcovr is installed. See
+ https://github.com/linux-test-project/lcov/issues/168 and
+ https://github.com/mesonbuild/meson/issues/6747
+
+ To create the coverage target add ``-Db_coverage=true`` to your build configuration.
+ After executing the tests, you can run ::
+
+ ninja -C <builddir> coverage
+
+ to generate the coverage report.
+
+lcov / llvm
+ https://clang.llvm.org/docs/SourceBasedCodeCoverage.html
+ Make sure that you are using `clang` as compiler, e.g. by setting `CC=clang` during configuration.
+ Beside that you need to add ``-Dllvm_cov=enabled`` to your build configuration ::
+
+ CC=clang meson setup -Dllvm_cov=enable <builddir>
+ meson test -C <builddir>
+ ninja -C <builddir> llvm-cov-tests
+
+For additional information see `the meson documentation <https://mesonbuild.com/Unit-tests.html#coverage>`_
+
+
+Installing
+----------
+To install flashrom and documentation, run::
+
+ meson install -C <builddir>
+
+This will install flashrom under the PREFIX selected in the configuration phase. Default is ``/usr/local``.
+
+To install into a different directory use DESTDIR, like this::
+
+ DESTDIR=/your/destination/directory meson install -C <your_build_dir>
+
+You can also set the prefix during configuration with::
+
+ meson setup --prefix <DESTDIR> <your_build_dir>
+
+Create distribution package
+---------------------------
+To create a distribution tarball from your ``builddir``, run::
+
+ meson dist -C <builddir>
+
+This will collect all git tracked files and pack them into an archive.
+
+Current flashrom version is in the VERSION file. To release a new flashrom
+version you need to change VERSION file and tag the changing commit.
diff --git a/doc/dev_guide/building_with_make.rst b/doc/dev_guide/building_with_make.rst
new file mode 100644
index 000000000..710aad3d1
--- /dev/null
+++ b/doc/dev_guide/building_with_make.rst
@@ -0,0 +1,195 @@
+Building with make
+==================
+
+TLDR
+----
+
+::
+
+ make
+ make install
+
+Build instructions
+------------------
+
+**To build flashrom you need to install the following software:**
+
+ * C compiler (GCC / clang)
+ * pkg-config
+
+ * pciutils+libpci (if you want support for mainboard or PCI device flashing)
+ * libusb (if you want FT2232, Dediprog or USB-Blaster support)
+ * libftdi (if you want FT2232 or USB-Blaster support)
+ * libjaylink (if you want support for SEGGER J-Link and compatible devices)
+ * NI-845x driver & library package (if you want support for NI-845x devices; uses a proprietary driver)
+
+**Linux et al:**
+
+ * pciutils / libpci
+ * pciutils-devel / pciutils-dev / libpci-dev
+ * zlib-devel / zlib1g-dev (needed if libpci was compiled with libz support)
+
+**On FreeBSD, you need the following ports:**
+
+ * devel/gmake
+ * devel/libpci
+
+**On OpenBSD, you need the following ports:**
+
+ * devel/gmake
+ * sysutils/pciutils
+
+**To compile on Linux, use**::
+
+ make
+
+**To compile on FreeBSD, OpenBSD or DragonFly BSD, use**::
+
+ gmake
+
+**To compile on Nexenta, use**::
+
+ make
+
+**To compile on Solaris, use**::
+
+ gmake LDFLAGS="-L$pathtolibpci" CC="gcc -I$pathtopciheaders" CFLAGS=-O2
+
+**To compile on NetBSD (with pciutils, libftdi, libusb installed in /usr/pkg/), use**::
+
+ gmake
+
+**To compile and run on Darwin/Mac OS X:**
+
+Install DirectHW from coresystems GmbH.
+DirectHW is available at https://www.coreboot.org/DirectHW .
+
+**To compile on Windows:**
+
+Install MSYS tools (and the NI-845x drivers if desired) as described in
+:ref:`installing-dependencies`.
+
+To build with support for NI-845x::
+
+ make HAS_LIB_NI845X=yes CONFIG_NI845X_SPI=yes
+
+**To cross-compile on Linux for DOS:**
+
+Get packages of the DJGPP cross compiler and install them:
+
+ * djgpp-filesystem djgpp-gcc djgpp-cpp djgpp-runtime djgpp-binutils
+
+As an alternative, the DJGPP web site offers packages for download as well:
+
+ * djcross-binutils-2.29.1-1ap.x86_64.rpm
+ * djcross-gcc-7.2.0-1ap.x86_64.rpm
+ * djcrx-2.05-5.x86_64.rpm
+
+The cross toolchain packages for your distribution may have slightly different
+names (look for packages named *djgpp*).
+
+Alternatively, you could use a script to build it from scratch:
+https://github.com/andrewwutw/build-djgpp
+
+You will need the libpci and libgetopt library source trees and
+their compiled static libraries and header files installed in some
+directory say libpci-libgetopt/, which will be later specified with
+LIBS_BASE parameter during flashrom compilation. Easiest way to
+handle it is to put pciutils, libgetopt and flashrom directories
+in one subdirectory. There will be an extra subdirectory libpci-libgetopt
+created, which will contain compiled libpci and libgetopt.
+
+Download pciutils 3.5.6 and apply https://flashrom.org/File:Pciutils-3.5.6.patch.gz
+Compile pciutils, using following command line::
+
+ make ZLIB=no DNS=no HOST=i386-djgpp-djgpp CROSS_COMPILE=i586-pc-msdosdjgpp- \
+ PREFIX=/ DESTDIR=$PWD/../libpci-libgetopt \
+ STRIP="--strip-program=i586-pc-msdosdjgpp-strip -s" install install-lib
+
+Download and compile with 'make' https://flashrom.org/File:Libgetopt.tar.gz
+
+Copy the libgetopt.a to ../libpci-libgetopt/lib and
+getopt.h to ../libpci-libgetopt/include
+
+Enter the flashrom directory::
+
+ make CC=i586-pc-msdosdjgpp-gcc STRIP=i586-pc-msdosdjgpp-strip LIBS_BASE=../libpci-libgetopt/ strip
+
+If you like, you can compress the resulting executable with UPX::
+
+ upx -9 flashrom.exe
+
+To run flashrom.exe, download https://flashrom.org/File:Csdpmi7b.zip and
+unpack CWSDPMI.EXE into the current directory or one in PATH.
+
+**To cross-compile on Linux for Windows:**
+
+Get packages of the MinGW cross compiler and install them::
+
+ mingw32-filesystem mingw32-cross-cpp mingw32-cross-binutils mingw32-cross-gcc
+ mingw32-runtime mingw32-headers
+
+The cross toolchain packages for your distribution may have slightly different
+names (look for packages named *mingw*).
+PCI-based programmers (internal etc.) are not supported on Windows.
+Run (change CC= and STRIP= settings where appropriate)::
+
+ make CC=i686-w64-mingw32-gcc STRIP=i686-w64-mingw32-strip
+
+**Processor architecture dependent features:**
+
+On non-x86 architectures a few programmers don't work (yet) because they
+use port-based I/O which is not directly available on non-x86. Those
+programmers will be disabled automatically if you run "make".
+
+**Compiler quirks:**
+
+If you are using clang and if you want to enable only one driver, you may hit an
+overzealous compiler warning from clang. Compile with "make WARNERROR=no" to
+force it to continue and enjoy.
+
+**Bindings:**
+
+Foreign function interface bindings for the rust language are included in the
+bindings folder. These are not compiled as part of the normal build process.
+See the readme under bindings/rust for more information.
+
+
+Installation
+------------
+
+In order to install flashrom and the manpage into /usr/local, type::
+
+ make install
+
+For installation in a different directory use DESTDIR, e.g. like this::
+
+ make DESTDIR=/usr install
+
+If you have insufficient permissions for the destination directory, use sudo
+by adding sudo in front of the commands above.
+
+
+Packaging
+---------
+
+To package flashrom and remove dependencies on Git, either use::
+
+ make export
+
+or::
+
+ make tarball
+
+``make export`` will export all flashrom files from the Git repository at
+revision HEAD into a directory named ``$EXPORTDIR/flashrom-$RELEASENAME``
+and will additionally add a ``versioninfo.inc`` file in that directory to
+contain the Git revision of the exported tree and a date for the manual
+page.
+
+``make tarball`` will simply tar up the result of make export and compress
+it with bzip2.
+
+The snapshot tarballs are the result of ``make tarball`` and require no
+further processing. Some git files (for example the rust bindings) are omitted
+from the tarball, as controlled by the .gitattributes files.
diff --git a/doc/dev_guide/development_guide.rst b/doc/dev_guide/development_guide.rst
new file mode 100644
index 000000000..40837a943
--- /dev/null
+++ b/doc/dev_guide/development_guide.rst
@@ -0,0 +1,342 @@
+=================
+Development Guide
+=================
+
+We welcome contributions from every human being, corporate entity or club.
+
+This document describes the rules and recommendations about the development, contribution and review processes.
+
+If you introduce new features (not flash chips, but stuff like partial
+programming, support for new external programmers, voltage handling, etc)
+please **discuss your plans** on the :ref:`mailing list` first. That way, we
+can avoid duplicated work and know about how flashrom internals need to be
+adjusted and you avoid frustration if there is some disagreement about the
+design.
+
+You can `look at the latest flashrom development efforts in Gerrit <https://review.coreboot.org/q/project:flashrom>`_.
+
+Set up the git repository and dev environment
+=============================================
+
+#. Clone git repository
+
+ * If using https: :code:`git clone "https://review.coreboot.org/flashrom"`
+ * If using ssh: :code:`git clone "ssh://<gerrit_username>@review.coreboot.org:29418/flashrom"`
+
+#. Follow the build guidelines to install dependencies :doc:`building_from_source`
+
+#. Install Git hooks: :code:`./util/git-hooks/install.sh`
+
+#. Add upstream as a remote:
+
+ * If using https: :code:`git remote add -f upstream https://review.coreboot.org/flashrom`
+ * If using ssh: :code:`git remote add -f upstream ssh://<gerrit_username>@review.coreboot.org:29418/flashrom`
+
+#. Check out a new local branch that tracks :code:`upstream/master`: :code:`git checkout -b <branch_name> upstream/master`
+
+#. Every patch is required to be signed-off (see also :ref:`sign-off`).
+ Set up your ``user.name`` and ``user.email`` in git config, and don't forget
+ to ``-s`` when creating a commit.
+
+#. See also build guidelines :doc:`building_from_source` and `git docs <https://git-scm.com/doc>`_
+
+Creating your patch
+===================
+
+In short, commit your changes with a descriptive message and remember to sign off
+on the commit (``git commit -s``).
+
+.. _commit-message:
+
+Commit message
+--------------
+
+Commit messages shall have the following format:
+
+.. code-block::
+
+ <component>: Short description (up to 72 characters)
+
+ This is a long description. Max width of each line in the description
+ is 72 characters. It is separated from the summary by a blank line. You
+ may skip the long description if the short description is sufficient,
+ for example "flashchips: Add FOO25Q128" to add FOO25Q128 chip support.
+
+ You may have multiple paragraphs in the long description, but please
+ do not write a novel here. For non-trivial changes you must explain
+ what your patch does, why, and how it was tested.
+
+ Finally, follow the sign-off procedure to add your sign-off!
+
+ Signed-off-by: Your Name <your@domain>
+
+Commit message should include:
+
+* Commit title
+* Commit description: explain what the patch is doing, or what it is fixing.
+* Testing information: how did you test the patch.
+* Signed-off-by line (see below :ref:`sign-off`)
+* If applicable, link to the ticket in the bugtracker `<https://ticket.coreboot.org/projects/flashrom>`_
+* Change-Id for Gerrit. If commit message doesn't have Change-Id, you forgot to install git hooks.
+
+.. _sign-off:
+
+Sign-off procedure
+^^^^^^^^^^^^^^^^^^
+
+We employ a similar sign-off procedure as the `Linux kernel developers
+<http://web.archive.org/web/20070306195036/http://osdlab.org/newsroom/press_releases/2004/2004_05_24_dco.html>`_
+do. Add a note such as
+
+:code:`Signed-off-by: Random J Developer <random@developer.example.org>`
+
+to your email/patch if you agree with the Developer's Certificate of Origin 1.1
+printed below. Read `this post on the LKML
+<https://lkml.org/lkml/2004/5/23/10>`_ for rationale (spoiler: SCO).
+
+You must use your known identity in the ``Signed-off-by`` line and in any
+copyright notices you add. Anonymous patches lack provenance and cannot be
+committed!
+
+Developer's Certificate of Origin 1.1
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+ By making a contribution to this project, I certify that:
+
+ (a) The contribution was created in whole or in part by me and I have
+ the right to submit it under the open source license indicated in the file; or
+
+ (b) The contribution is based upon previous work that, to the best of my
+ knowledge, is covered under an appropriate open source license and I have the
+ right under that license to submit that work with modifications, whether created
+ in whole or in part by me, under the same open source license (unless I am
+ permitted to submit under a different license), as indicated in the file; or
+
+ (c) The contribution was provided directly to me by some other person who
+ certified (a), (b) or (c) and I have not modified it; and
+
+ (d) In the case of each of (a), (b), or (c), I understand and agree that
+ this project and the contribution are public and that a record of the contribution
+ (including all personal information I submit with it, including my sign-off) is
+ maintained indefinitely and may be redistributed consistent with this project or the
+ open source license indicated in the file.
+
+.. note::
+
+ The `Developer's Certificate of Origin 1.1
+ <http://web.archive.org/web/20070306195036/http://osdlab.org/newsroom/press_releases/2004/2004_05_24_dco.html>`_
+ is licensed under the terms of the `Creative Commons Attribution-ShareAlike
+ 2.5 License <http://creativecommons.org/licenses/by-sa/2.5/>`_.
+
+Coding style
+------------
+
+Flashrom generally follows Linux kernel style:
+https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/coding-style.rst
+
+The notable exception is line length limit. Our guidelines are:
+
+* 80-columns soft limit for most code and comments. This is to encourage simple design and concise naming.
+* 112-columns hard limit. Use this to reduce line breaks in cases where they
+ harm grep-ability or overall readability, such as print statements and
+ function signatures. Don't abuse this for long variable/function names or
+ deep nesting.
+* Tables are the only exception to the hard limit and may be as long as needed
+ for practical purposes.
+
+Our guidelines borrow heavily from `coreboot coding style
+<https://doc.coreboot.org/contributing/coding_style.html>`_ and `coreboot Gerrit
+guidelines <https://doc.coreboot.org/contributing/gerrit_guidelines.html>`_,
+and most of them apply to flashrom as well. The really important part is about
+the :ref:`sign-off procedure <sign-off>`.
+
+We try to **reuse as much code as possible** and create new files only if
+absolutely needed, so if you find a function somewhere in the tree which
+already does what you want, please use it.
+
+Testing a patch
+---------------
+
+We expect the patch to be appropriately tested by the patch owner.
+Please add the testing information in commit message, for example that could be some of these:
+programmer you were using, programmer params, chip, OS, operations you were running
+(read/write/erase/verify), and anything else that is relevant.
+
+.. _working-with-gerrit:
+
+Working with Gerrit
+===================
+
+All of the patches and code reviews need to go via
+`Gerrit on review.coreboot.org <https://review.coreboot.org/#/q/project:flashrom>`_.
+While it is technically possible to send a patch to the mailing list, that patch
+still needs to be pushed to Gerrit by someone. We treat patches on the mailing list as a very
+exceptional situation. Normal process is to push a patch to Gerrit.
+Please read below for instructions and check `official Gerrit documentation <https://gerrit-review.googlesource.com/Documentation/>`_.
+
+Creating an account
+---------------------
+
+#. Go to https://review.coreboot.org/login and sign in using the credentials of
+ your choice.
+#. Edit your settings by clicking on the gear icon in the upper right corner.
+#. Set your Gerrit username (this may be the different from the username of an
+ external account you log in with).
+#. Add an e-mail address so that Gerrit can send notifications to you about
+ your patch.
+#. Upload an SSH public key, or click the button to generate an HTTPS password.
+
+.. _pushing-a-patch:
+
+Pushing a patch
+---------------
+
+To push patch to Gerrit, use the follow command: :code:`git push upstream HEAD:refs/for/master`.
+
+* If using HTTPS you will be prompted for the username and password you
+ set in the Gerrit UI.
+* If successful, the Gerrit URL for your patch will be shown in the output.
+
+There is an option to add a topic to the patch. For one-off standalone patches this
+is not necessary. However if your patch is a part of a larger effort, especially if the
+work involves multiple contributors, it can be useful to mark that the patch belongs
+to a certain topic.
+
+Adding a topic makes it easy to search "all the patches by the topic", even if the patches
+have been authored by multiple people.
+
+To add a topic, push with the command: :code:`git push upstream HEAD:refs/for/master%topic=example_topic`.
+Alternatively, you can add a topic from a Gerrit UI after the patch in pushed
+(on the top-left section) of patch UI.
+
+Adding reviewers to the patch
+-----------------------------
+
+After pushing the patch, ideally try to make sure there are some reviewers added to your patch.
+
+flashrom has MAINTAINERS file with people registered for some areas of the code. People who
+are in MAINTAINERS file will be automatically added as reviewers if the patch touches that
+area. However, not all areas are covered in the file, and it is possible that for the patch you
+sent no one is added automatically.
+
+If you know someone in the dev community who can help with patch review, add the person(s) you know.
+
+In general, it's a good idea to add someone who has a knowledge of whatever the patch is doing,
+even if the person has not been added automatically.
+
+If you are new, and don't know anyone, and no one has been added automatically: you can add
+Anastasia Klimchuk (aklm) as a reviewer.
+
+Going through code reviews
+--------------------------
+
+You will likely get some comments on your patch, and you will need to fix the comments.
+After doing the work locally, amend your commit ``git commit --amend -s`` and push to Gerrit again.
+Check that Change-Id in commit message stays the same. This way Gerrit knows your change belongs
+to the same patch, and will upload new change as new patchset for the same patch.
+
+After uploading the work, go through comments and respond to them. Mark as Done the ones you done
+and mark them as resolved. If there is something that is impossible to do, or maybe you have more questions,
+or maybe you are not sure what you are asked about: respond to a comment **without marking it as resolved**.
+
+It is completely fine to ask a clarifying questions if you don't understand what the comment is asking you to do.
+If is also fine to explain why a comment can't be done, if you think it can't be done.
+
+The patch reviews may take some time, but please don't get discouraged.
+We have quite high standards regarding code quality.
+
+Initial review should include a broad indication of acceptance or rejection of
+the idea/rationale/motivation or the implementation
+
+In general, reviews should focus on the architectural changes and things that
+affect flashrom as a whole. This includes (but is by no means limited to)
+changes in APIs and types, safety, portability, extensibility, and
+maintainability. The purpose of reviews is not to create perfect patches, but
+to steer development in the right direction and produce consensus within the
+community. The goal of each patch should be to improve the state of the project
+- it does not need to fix all problems of the respective field perfectly.
+
+ New contributors may need more detailed advices and should be told about
+ minor issues like formatting problems more precisely. The result of a review
+ should either be an accepted patch or a guideline how the existing code
+ should be changed to be eventually accepted.
+
+To get an idea whether the patch is ready or not, please check :ref:`merge-checklist`.
+
+If you sent a patch and later lost interest or no longer have time to follow up on code review,
+please add a comment saying so. Then, if any of our maintainers are interested in finishing the work,
+they can take over the patch.
+
+Downloading patch from Gerrit
+-----------------------------
+
+Sometimes you may need to download a patch into your local repository. This can be needed for example:
+
+* if you want to test someone else's patch,
+* if multiple developers are collaborating on a patch,
+* if you are continuing someone else's work, when original author left or unable to continue.
+
+First prepare local repository: sync to head or to desired tag / commit.
+
+Open patch in Gerrit, open "three dot" menu on top-right, open Download patch. Copy Cherry-pick command (pick
+the relevant tab for you: anonymous http / http / ssh) and run the copied command in your local repo.
+
+Now you have the commit locally and can do the testing or futher developing. To upload your local changes,
+push patch to Gerrit again (see :ref:`pushing-a-patch`).
+
+Make sure people involved in the patch agree that you are pushing new version of someone else's patch,
+so this does not come at a surprise for an original author.
+
+Merging patches
+---------------
+
+Merging to branches is limited to the "flashrom developers" group on Gerrit (see also :doc:`/about_flashrom/team`).
+
+The list of requirements for the patch to be ready for merging is below, see :ref:`merge-checklist`.
+Some of the requirements are enforced by Gerrit, but not all of them. In general, a person who clicks
+Submit button is responsible to go through Merge checklist. Code reviewers should be aware of the checklist
+as well.
+
+Patch owners can use the checklist to detect whether the patch is ready for merging or not.
+
+.. _merge-checklist:
+
+Merge checklist
+^^^^^^^^^^^^^^^
+
+#. Every patch has to be reviewed and needs at least one +2 that was not given by the commit's author.
+ Ideally, people who were actively reviewing the patch and adding comments, would be the ones approving it.
+#. If a patch is authored by more than one person (Co-developed-by), each author may +2 the other author's changes.
+#. Patch needs to get Verified +1 vote, typically from Jenkins build bot. This means the patch builds successfully
+ and all unit tests pass.
+#. Commit message should have Signed-off-by line, see :ref:`sign-off` and align with the rest
+ of the rules for :ref:`commit-message`
+#. All the comments need to be addressed, especially if there was a negative vote in the process of review (-1 or -2).
+#. flashrom developers are people from literally all around the planet, and various timezones. We usually wait
+ for 3 days (3 * 24hours) after the patch is fully approved just in case of last minute concerns from all timezones.
+#. In the case of emergency, merging should not take place within less than 24 hours after the review
+ started (i.e. the first message by a reviewer on Gerrit).
+
+To help search for patches which are potential candidates for merging, you can try using this search in Gerrit::
+
+ status:open project:flashrom -is:wip -label:Verified-1 label:Verified+1 -label:Code-Review<0 age:3d is:mergeable is:submittable -has:unresolved
+
+Note the search is not a replacement for Merge checklist, but it can help find candidates for merging.
+
+Bugtracker
+==========
+
+We have a bugtracker on `<https://ticket.coreboot.org/projects/flashrom>`_.
+Anyone can view tickets, but to be able to create/update/assign tickets you need an account.
+
+Mirrors
+========
+
+The only official repository is https://review.coreboot.org/flashrom ; GitHub and GitLab are just mirrors.
+**Reviewers do not look at pull requests** on mirrors.
+Even if pull requests were automatically transferred to Gerrit,
+requirements such as :ref:`sign-off` still present a problem.
+
+The quickest and best way to get your patch reviewed and merged is by sending
+it to review.coreboot.org (see :ref:`working-with-Gerrit`). Conveniently, you can use your GitHub, GitLab or
+Google account as an OAuth2 `login method <https://review.coreboot.org/login>`_.
diff --git a/doc/dev_guide/index.rst b/doc/dev_guide/index.rst
new file mode 100644
index 000000000..57cd8468c
--- /dev/null
+++ b/doc/dev_guide/index.rst
@@ -0,0 +1,9 @@
+Developers documentation
+========================
+
+.. toctree::
+ :maxdepth: 1
+
+ building_from_source
+ building_with_make
+ development_guide
diff --git a/doc/documentation_license.rst b/doc/documentation_license.rst
new file mode 100644
index 000000000..ebadeb77d
--- /dev/null
+++ b/doc/documentation_license.rst
@@ -0,0 +1,296 @@
+=====================
+Documentation license
+=====================
+
+Files under doc/ are licensed under CC-BY 4.0 terms, printed below.
+
+Attribution 4.0 International
+=============================
+
+Creative Commons Corporation ("Creative Commons") is not a law firm and does not provide
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+By exercising the Licensed Rights (defined below), You accept and agree to be bound by the
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+unless expressly agreed.
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+separate from and independent of the terms and conditions of this Public License.
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+restrict, or impose conditions on any use of the Licensed Material that could lawfully be made without
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+
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+be reformed, it shall be severed from this Public License without affecting the enforceability of the
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+
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+expressly agreed to by the Licensor.
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+
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diff --git a/doc/how_to_add_docs.rst b/doc/how_to_add_docs.rst
new file mode 100644
index 000000000..0b32acbd2
--- /dev/null
+++ b/doc/how_to_add_docs.rst
@@ -0,0 +1,35 @@
+How to add or update docs
+=========================
+
+To add or update a documentation page, you need to create or modify
+an ``.rst`` file in the ``/doc`` directory and send a patch for
+review.
+
+People who are registered in MAINTAINERS file for doc/ directory will
+be automatically added to the patch as reviewers. However, you are
+very welcome to add more reviewers who know the subject. In fact, it
+is always a good idea to add someone who has knowledge of the specific
+area you are documenting.
+
+We are using Sphinx doc engine for documentation (see
+https://www.sphinx-doc.org/) and reStructured Text format for content.
+reStructuredText Primer page has more details
+https://www.sphinx-doc.org/en/master/usage/restructuredtext/basics.html#restructuredtext-primer
+
+Brand new page needs to be added to the appropriate ``index.rst`` file
+under ``/doc`` directory (that could be a root index file or nested one).
+
+To test your changes, build flashrom with documentation and open
+generated ``.html`` file in the browser. Generated ``.html`` files are
+in meson ``builddir/doc/html`` directory.
+
+Misc questions
+--------------
+
+* We use CC-BY-4.0 license for documentation.
+* Writing style can be formal or informal, it's mostly up to you, the
+ important thing is to make the text clear, readable and unambiguous. You
+ can insert images if this really helps the readers to understand the
+ instructions.
+* Documentation should be relevant to either flashrom usage or flashrom
+ development
diff --git a/doc/index.rst b/doc/index.rst
new file mode 100644
index 000000000..194393434
--- /dev/null
+++ b/doc/index.rst
@@ -0,0 +1,22 @@
+.. flashrom documentation master file, created by
+ sphinx-quickstart on Mon Jan 30 17:34:19 2023.
+ You can adapt this file completely to your liking, but it should at least
+ contain the root `toctree` directive.
+
+.. image:: logo/flashrom_logo.png
+ :alt: flashrom logo
+
+.. toctree::
+ :hidden:
+
+ dev_guide/index
+ classic_cli_manpage
+ contact
+ about_flashrom/index
+ how_to_add_docs
+ documentation_license
+ Old wiki website <https://wiki.flashrom.org/>
+
+.. include:: intro.rst
+
+.. include:: ../README.rst
diff --git a/doc/intro.rst b/doc/intro.rst
new file mode 100644
index 000000000..b1fe99aed
--- /dev/null
+++ b/doc/intro.rst
@@ -0,0 +1,34 @@
+**flashrom** is a utility for identifying, reading, writing, verifying and erasing flash
+chips. It is designed to flash BIOS/EFI/coreboot/firmware/optionROM images on mainboards,
+network/graphics/storage controller cards, and various other programmer devices.
+
+* Supports more than 476 flash chips, 291 chipsets, 500 mainboards, 79 PCI devices,
+ 17 USB devices and various parallel/serial port-based programmers.
+* Supports parallel, LPC, FWH and SPI flash interfaces and various chip packages (DIP32,
+ PLCC32, DIP8, SO8/SOIC8, TSOP32, TSOP40, TSOP48, BGA and more).
+* No physical access needed, root access is sufficient (not needed for some programmers).
+* No bootable floppy disk, bootable CD-ROM or other media needed.
+* No keyboard or monitor needed. Simply reflash remotely via SSH.
+* No instant reboot needed. Reflash your chip in a running system, verify it, be happy.
+ The new firmware will be present next time you boot.
+* Crossflashing and hotflashing is possible as long as the flash chips are electrically
+ and logically compatible (same protocol). Great for recovery.
+* Scriptability. Reflash a whole pool of identical machines at the same time from the
+ command line. It is recommended to check flashrom output and error codes.
+* Speed. flashrom is often much faster than most vendor flash tools.
+* Portability. Supports DOS, Linux, FreeBSD (including Debian/kFreeBSD), NetBSD, OpenBSD,
+ DragonFlyBSD, anything Solaris-like, Mac OS X, and other Unix-like OSes as well as GNU Hurd.
+ Partial Windows support is available (no internal programmer support at the moment, hence
+ no "BIOS flashing").
+
+.. todo:: Convert Technology page and add links here
+
+.. container:: danger, admonition
+
+ **Emergency help**
+
+ IMPORTANT: If something went wrong during flashing, do NOT turn off/reboot your computer.
+ Instead, let us help you recover. We can be contacted via `IRC <https://www.flashrom.org/contact.html#irc>`_
+ (#flashrom on `libera.chat <irc://irc.libera.chat/#flashrom>`_, `webchat <https://web.libera.chat/#flashrom>`_),
+ `Discord <https://www.flashrom.org/contact.html#discord>`_, or `email <https://www.flashrom.org/contact.html#mailing-list-1>`_.
+ Please allow some time until someone responds, we're all volunteers.
diff --git a/doc/logo/COPYING b/doc/logo/COPYING
new file mode 100644
index 000000000..3a7d190ce
--- /dev/null
+++ b/doc/logo/COPYING
@@ -0,0 +1,12 @@
+The flashrom logo and icons in this directory were originally designed by Stefan Tauner in 2015.
+The lettering is based on the "Free Mono" font of the GNU FreeFont family.
+The SOIC chip seen in the lettering is based on the SOIC08 narrow STL CAD file from
+https://grabcad.com/library/soic-package-narrow-8-10-14-and-16-pins-1
+It was rendered by Blender with the Freestyle SVG plugin from
+https://github.com/hvfrancesco/freestylesvg
+
+All source image files within this directory (i.e. all with names ending with ".svg" or ."xcf")
+are licensed under the Creative Commons Attribution-NoDerivatives 4.0 license (CC BY-ND 4.0):
+http://creativecommons.org/licenses/by-nd/4.0/
+All image files produced from the source image files mentioned above and included in this
+directory are in the public domain.
diff --git a/doc/logo/flashrom_icon_bw.svg b/doc/logo/flashrom_icon_bw.svg
new file mode 100644
index 000000000..e19996e41
--- /dev/null
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diff --git a/doc/meson.build b/doc/meson.build
new file mode 100644
index 000000000..aca73d8a9
--- /dev/null
+++ b/doc/meson.build
@@ -0,0 +1,36 @@
+
+sphinx = find_program('sphinx-build', native : true, required : get_option('man-pages').enabled() or get_option('documentation').enabled())
+
+man_pages = [
+ 'flashrom.8'
+]
+
+if sphinx.found()
+ if get_option('man-pages').auto() or get_option('man-pages').enabled()
+ man_outputs = []
+ foreach page : man_pages
+ man_outputs += 'man' + page.substring(-1)
+ endforeach
+
+ custom_target(
+ 'man-pages',
+ command : [sphinx, '-b', 'man', '-q', '-d', '@PRIVATE_DIR@', '-Drelease=' + flashrom_version,'@CURRENT_SOURCE_DIR@', '@OUTDIR@'],
+ build_always_stale : true, # sphinx handles rebuilds
+ output : man_outputs,
+ install : true,
+ install_dir : get_option('mandir'),
+ )
+ endif
+
+ if get_option('documentation').auto() or get_option('documentation').enabled()
+ custom_target(
+ 'documentation',
+ command : [sphinx, '-b', 'html', '-q', '-d', '@PRIVATE_DIR@', '-Drelease=' + flashrom_version,'@CURRENT_SOURCE_DIR@', '@OUTDIR@/html'],
+ build_always_stale : true, # sphinx handles rebuilds
+ output : 'html',
+ install : true,
+ install_dir : get_option('datadir') + '/doc/flashrom'
+ )
+ endif
+
+endif