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Diffstat (limited to 'nicintel_spi.c')
-rw-r--r--nicintel_spi.c182
1 files changed, 121 insertions, 61 deletions
diff --git a/nicintel_spi.c b/nicintel_spi.c
index 1173ef772..2821d23a0 100644
--- a/nicintel_spi.c
+++ b/nicintel_spi.c
@@ -34,7 +34,8 @@
#include <unistd.h>
#include "flash.h"
#include "programmer.h"
-#include "hwaccess.h"
+#include "hwaccess_physmap.h"
+#include "platform/pci.h"
#define PCI_VENDOR_ID_INTEL 0x8086
#define MEMMAP_SIZE getpagesize()
@@ -73,11 +74,11 @@
// #define FL_BUSY 30
// #define FL_ER 31
-#define BIT(x) (1<<(x))
-
-static uint8_t *nicintel_spibar;
+struct nicintel_spi_data {
+ uint8_t *spibar;
+};
-const struct dev_entry nics_intel_spi[] = {
+static const struct dev_entry nics_intel_spi[] = {
{PCI_VENDOR_ID_INTEL, 0x105e, OK, "Intel", "82571EB Gigabit Ethernet Controller"},
{PCI_VENDOR_ID_INTEL, 0x1076, OK, "Intel", "82541GI Gigabit Ethernet Controller"},
{PCI_VENDOR_ID_INTEL, 0x107c, OK, "Intel", "82541PI Gigabit Ethernet Controller"},
@@ -107,90 +108,125 @@ const struct dev_entry nics_intel_spi[] = {
{0},
};
-static void nicintel_request_spibus(void)
+static void nicintel_request_spibus(void *spi_data)
{
+ struct nicintel_spi_data *data = spi_data;
uint32_t tmp;
- tmp = pci_mmio_readl(nicintel_spibar + FLA);
+ tmp = pci_mmio_readl(data->spibar + FLA);
tmp |= BIT(FL_REQ);
- pci_mmio_writel(tmp, nicintel_spibar + FLA);
+ pci_mmio_writel(tmp, data->spibar + FLA);
/* Wait until we are allowed to use the SPI bus. */
- while (!(pci_mmio_readl(nicintel_spibar + FLA) & BIT(FL_GNT))) ;
+ while (!(pci_mmio_readl(data->spibar + FLA) & BIT(FL_GNT))) ;
}
-static void nicintel_release_spibus(void)
+static void nicintel_release_spibus(void *spi_data)
{
+ struct nicintel_spi_data *data = spi_data;
uint32_t tmp;
- tmp = pci_mmio_readl(nicintel_spibar + FLA);
+ tmp = pci_mmio_readl(data->spibar + FLA);
tmp &= ~BIT(FL_REQ);
- pci_mmio_writel(tmp, nicintel_spibar + FLA);
+ pci_mmio_writel(tmp, data->spibar + FLA);
}
-static void nicintel_bitbang_set_cs(int val)
+static void nicintel_bitbang_set_cs(int val, void *spi_data)
{
+ struct nicintel_spi_data *data = spi_data;
uint32_t tmp;
- tmp = pci_mmio_readl(nicintel_spibar + FLA);
+ tmp = pci_mmio_readl(data->spibar + FLA);
tmp &= ~BIT(FL_CS);
tmp |= (val << FL_CS);
- pci_mmio_writel(tmp, nicintel_spibar + FLA);
+ pci_mmio_writel(tmp, data->spibar + FLA);
}
-static void nicintel_bitbang_set_sck(int val)
+static void nicintel_bitbang_set_sck(int val, void *spi_data)
{
+ struct nicintel_spi_data *data = spi_data;
uint32_t tmp;
- tmp = pci_mmio_readl(nicintel_spibar + FLA);
+ tmp = pci_mmio_readl(data->spibar + FLA);
tmp &= ~BIT(FL_SCK);
tmp |= (val << FL_SCK);
- pci_mmio_writel(tmp, nicintel_spibar + FLA);
+ pci_mmio_writel(tmp, data->spibar + FLA);
}
-static void nicintel_bitbang_set_mosi(int val)
+static void nicintel_bitbang_set_mosi(int val, void *spi_data)
{
+ struct nicintel_spi_data *data = spi_data;
uint32_t tmp;
- tmp = pci_mmio_readl(nicintel_spibar + FLA);
+ tmp = pci_mmio_readl(data->spibar + FLA);
tmp &= ~BIT(FL_SI);
tmp |= (val << FL_SI);
- pci_mmio_writel(tmp, nicintel_spibar + FLA);
+ pci_mmio_writel(tmp, data->spibar + FLA);
}
-static int nicintel_bitbang_get_miso(void)
+static void nicintel_bitbang_set_sck_set_mosi(int sck, int mosi, void *spi_data)
{
+ struct nicintel_spi_data *data = spi_data;
uint32_t tmp;
- tmp = pci_mmio_readl(nicintel_spibar + FLA);
+ tmp = pci_mmio_readl(data->spibar + FLA);
+ tmp &= ~BIT(FL_SCK);
+ tmp &= ~BIT(FL_SI);
+ tmp |= (sck << FL_SCK);
+ tmp |= (mosi << FL_SI);
+ pci_mmio_writel(tmp, data->spibar + FLA);
+}
+
+static int nicintel_bitbang_get_miso(void *spi_data)
+{
+ struct nicintel_spi_data *data = spi_data;
+ uint32_t tmp;
+
+ tmp = pci_mmio_readl(data->spibar + FLA);
tmp = (tmp >> FL_SO) & 0x1;
return tmp;
}
+static int nicintel_bitbang_set_sck_get_miso(int sck, void *spi_data)
+{
+ struct nicintel_spi_data *data = spi_data;
+ uint32_t tmp;
+
+ tmp = pci_mmio_readl(data->spibar + FLA);
+ tmp &= ~BIT(FL_SCK);
+ tmp |= (sck << FL_SCK);
+ pci_mmio_writel(tmp, data->spibar + FLA);
+ return (tmp >> FL_SO) & 0x1;
+}
+
static const struct bitbang_spi_master bitbang_spi_master_nicintel = {
- .set_cs = nicintel_bitbang_set_cs,
- .set_sck = nicintel_bitbang_set_sck,
- .set_mosi = nicintel_bitbang_set_mosi,
- .get_miso = nicintel_bitbang_get_miso,
- .request_bus = nicintel_request_spibus,
- .release_bus = nicintel_release_spibus,
- .half_period = 1,
+ .set_cs = nicintel_bitbang_set_cs,
+ .set_sck = nicintel_bitbang_set_sck,
+ .set_mosi = nicintel_bitbang_set_mosi,
+ .set_sck_set_mosi = nicintel_bitbang_set_sck_set_mosi,
+ .set_sck_get_miso = nicintel_bitbang_set_sck_get_miso,
+ .get_miso = nicintel_bitbang_get_miso,
+ .request_bus = nicintel_request_spibus,
+ .release_bus = nicintel_release_spibus,
+ .half_period = 1,
};
-static int nicintel_spi_shutdown(void *data)
+static int nicintel_spi_shutdown(void *spi_data)
{
+ struct nicintel_spi_data *data = spi_data;
uint32_t tmp;
/* Disable writes manually. See the comment about EECD in nicintel_spi_init() for details. */
- tmp = pci_mmio_readl(nicintel_spibar + EECD);
+ tmp = pci_mmio_readl(data->spibar + EECD);
tmp &= ~FLASH_WRITES_ENABLED;
tmp |= FLASH_WRITES_DISABLED;
- pci_mmio_writel(tmp, nicintel_spibar + EECD);
+ pci_mmio_writel(tmp, data->spibar + EECD);
+ free(data);
return 0;
}
-static int nicintel_spi_82599_enable_flash(void)
+static int nicintel_spi_82599_enable_flash(struct nicintel_spi_data *data)
{
uint32_t tmp;
@@ -199,56 +235,61 @@ static int nicintel_spi_82599_enable_flash(void)
* but other bits with side effects as well. Those other bits must be
* left untouched.
*/
- tmp = pci_mmio_readl(nicintel_spibar + EECD);
+ tmp = pci_mmio_readl(data->spibar + EECD);
tmp &= ~FLASH_WRITES_DISABLED;
tmp |= FLASH_WRITES_ENABLED;
- pci_mmio_writel(tmp, nicintel_spibar + EECD);
+ pci_mmio_writel(tmp, data->spibar + EECD);
/* test if FWE is really set to allow writes */
- tmp = pci_mmio_readl(nicintel_spibar + EECD);
+ tmp = pci_mmio_readl(data->spibar + EECD);
if ( (tmp & FLASH_WRITES_DISABLED) || !(tmp & FLASH_WRITES_ENABLED) ) {
msg_perr("Enabling flash write access failed.\n");
return 1;
}
- if (register_shutdown(nicintel_spi_shutdown, NULL))
+ if (register_shutdown(nicintel_spi_shutdown, data))
return 1;
return 0;
}
-static int nicintel_spi_i210_enable_flash(void)
+static int nicintel_spi_i210_shutdown(void *data)
+{
+ free(data);
+ return 0;
+}
+
+static int nicintel_spi_i210_enable_flash(struct nicintel_spi_data *data)
{
uint32_t tmp;
- tmp = pci_mmio_readl(nicintel_spibar + FLA);
+ tmp = pci_mmio_readl(data->spibar + FLA);
if (tmp & BIT(FL_LOCKED)) {
msg_perr("Flash is in Secure Mode. Abort.\n");
return 1;
}
- if (!(tmp & BIT(FL_ABORT)))
- return 0;
+ if (tmp & BIT(FL_ABORT)) {
+ tmp |= BIT(FL_CLR_ERR);
+ pci_mmio_writel(tmp, data->spibar + FLA);
+ tmp = pci_mmio_readl(data->spibar + FLA);
+ if (!(tmp & BIT(FL_ABORT))) {
+ msg_perr("Unable to clear Flash Access Error. Abort\n");
+ return 1;
+ }
+ }
- tmp |= BIT(FL_CLR_ERR);
- pci_mmio_writel(tmp, nicintel_spibar + FLA);
- tmp = pci_mmio_readl(nicintel_spibar + FLA);
- if (!(tmp & BIT(FL_ABORT))) {
- msg_perr("Unable to clear Flash Access Error. Abort\n");
+ if (register_shutdown(nicintel_spi_i210_shutdown, data))
return 1;
- }
return 0;
}
-int nicintel_spi_init(void)
+static int nicintel_spi_init(const struct programmer_cfg *cfg)
{
struct pci_dev *dev = NULL;
- if (rget_io_perms())
- return 1;
-
- dev = pcidev_init(nics_intel_spi, PCI_BASE_ADDRESS_0);
+ dev = pcidev_init(cfg, nics_intel_spi, PCI_BASE_ADDRESS_0);
if (!dev)
return 1;
@@ -256,25 +297,44 @@ int nicintel_spi_init(void)
if (!io_base_addr)
return 1;
+ struct nicintel_spi_data *data = calloc(1, sizeof(*data));
+ if (!data) {
+ msg_perr("Unable to allocate space for SPI master data\n");
+ return 1;
+ }
+
if ((dev->device_id & 0xfff0) == 0x1530) {
- nicintel_spibar = rphysmap("Intel I210 Gigabit w/ SPI flash", io_base_addr + 0x12000,
+ data->spibar = rphysmap("Intel I210 Gigabit w/ SPI flash", io_base_addr + 0x12000,
MEMMAP_SIZE);
- if (!nicintel_spibar || nicintel_spi_i210_enable_flash())
+ if (!data->spibar || nicintel_spi_i210_enable_flash(data)) {
+ free(data);
return 1;
+ }
} else if (dev->device_id < 0x10d8) {
- nicintel_spibar = rphysmap("Intel Gigabit NIC w/ SPI flash", io_base_addr,
+ data->spibar = rphysmap("Intel Gigabit NIC w/ SPI flash", io_base_addr,
MEMMAP_SIZE);
- if (!nicintel_spibar || nicintel_spi_82599_enable_flash())
+ if (!data->spibar || nicintel_spi_82599_enable_flash(data)) {
+ free(data);
return 1;
+ }
} else {
- nicintel_spibar = rphysmap("Intel 10 Gigabit NIC w/ SPI flash", io_base_addr + 0x10000,
+ data->spibar = rphysmap("Intel 10 Gigabit NIC w/ SPI flash", io_base_addr + 0x10000,
MEMMAP_SIZE);
- if (!nicintel_spibar || nicintel_spi_82599_enable_flash())
+ if (!data->spibar || nicintel_spi_82599_enable_flash(data)) {
+ free(data);
return 1;
+ }
}
- if (register_spi_bitbang_master(&bitbang_spi_master_nicintel))
- return 1;
+ if (register_spi_bitbang_master(&bitbang_spi_master_nicintel, data))
+ return 1; /* shutdown function does cleanup */
return 0;
}
+
+const struct programmer_entry programmer_nicintel_spi = {
+ .name = "nicintel_spi",
+ .type = PCI,
+ .devs.dev = nics_intel_spi,
+ .init = nicintel_spi_init,
+};
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-04 03:58:45 +0000