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-rw-r--r--sb600spi.c263
1 files changed, 140 insertions, 123 deletions
diff --git a/sb600spi.c b/sb600spi.c
index ef9da4b1a..cec7e0a59 100644
--- a/sb600spi.c
+++ b/sb600spi.c
@@ -18,14 +18,14 @@
* GNU General Public License for more details.
*/
-#if defined(__i386__) || defined(__x86_64__)
-
+#include <stdbool.h>
#include <string.h>
#include <stdlib.h>
#include "flash.h"
#include "programmer.h"
-#include "hwaccess.h"
+#include "hwaccess_physmap.h"
#include "spi.h"
+#include "platform/pci.h"
/* This struct is unused, but helps visualize the SB600 SPI BAR layout.
*struct sb600_spi_controller {
@@ -40,7 +40,6 @@
*};
*/
-static uint8_t *sb600_spibar = NULL;
enum amd_chipset {
CHIPSET_AMD_UNKNOWN,
CHIPSET_SB6XX,
@@ -55,13 +54,18 @@ enum amd_chipset {
#define FIFO_SIZE_OLD 8
#define FIFO_SIZE_YANGTZE 71
+#define SPI100_CMD_CODE_REG 0x45
+#define SPI100_CMD_TRIGGER_REG 0x47
+#define SPI100_EXECUTE_CMD (1 << 7)
+
struct sb600spi_data {
struct flashctx *flash;
+ uint8_t *spibar;
};
static int find_smbus_dev_rev(uint16_t vendor, uint16_t device)
{
- struct pci_dev *smbus_dev = pci_dev_find(vendor, device);
+ struct pci_dev *smbus_dev = pcidev_find(vendor, device);
if (!smbus_dev) {
msg_pdbg("No SMBus device with ID %04X:%04X found.\n", vendor, device);
msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n");
@@ -127,9 +131,9 @@ static enum amd_chipset determine_generation(struct pci_dev *dev)
* found on both Stoney Ridge and Zen platforms.
*
* The revisions I have found by searching various lspci
- * outputs are as follows: 0x4b, 0x59 & 0x61.
+ * outputs are as follows: 0x4b, 0x59, 0x61 & 0x71.
*/
- } else if (rev == 0x4b || rev == 0x51 || rev == 0x59 || rev == 0x61) {
+ } else if (rev == 0x4b || rev == 0x51 || rev == 0x59 || rev == 0x61 || rev == 0x71) {
msg_pdbg("Promontory (rev 0x%02x) detected.\n", rev);
return CHIPSET_PROMONTORY;
} else {
@@ -149,7 +153,7 @@ static enum amd_chipset determine_generation(struct pci_dev *dev)
return CHIPSET_AMD_UNKNOWN;
}
-static void reset_internal_fifo_pointer(void)
+static void reset_internal_fifo_pointer(uint8_t *sb600_spibar)
{
mmio_writeb(mmio_readb(sb600_spibar + 2) | 0x10, sb600_spibar + 2);
@@ -158,7 +162,7 @@ static void reset_internal_fifo_pointer(void)
msg_pspew("reset\n");
}
-static int compare_internal_fifo_pointer(uint8_t want)
+static int compare_internal_fifo_pointer(uint8_t want, uint8_t *sb600_spibar)
{
uint8_t have = mmio_readb(sb600_spibar + 0xd) & 0x07;
want %= FIFO_SIZE_OLD;
@@ -192,7 +196,7 @@ static int check_readwritecnt(const struct flashctx *flash, unsigned int writecn
return 0;
}
-static void execute_command(void)
+static void execute_command(uint8_t *sb600_spibar)
{
msg_pspew("Executing... ");
mmio_writeb(mmio_readb(sb600_spibar + 2) | 1, sb600_spibar + 2);
@@ -201,11 +205,23 @@ static void execute_command(void)
msg_pspew("done\n");
}
+static void execute_spi100_command(uint8_t *sb600_spibar)
+{
+ msg_pspew("Executing... ");
+ mmio_writeb(mmio_readb(sb600_spibar + SPI100_CMD_TRIGGER_REG) | SPI100_EXECUTE_CMD,
+ sb600_spibar + SPI100_CMD_TRIGGER_REG);
+ while (mmio_readb(sb600_spibar + SPI100_CMD_TRIGGER_REG) & SPI100_CMD_TRIGGER_REG)
+ ;
+ msg_pspew("done\n");
+}
+
static int sb600_spi_send_command(const struct flashctx *flash, unsigned int writecnt,
unsigned int readcnt,
const unsigned char *writearr,
unsigned char *readarr)
{
+ struct sb600spi_data *sb600_data = flash->mst->spi.data;
+ uint8_t *sb600_spibar = sb600_data->spibar;
/* First byte is cmd which can not be sent through the FIFO. */
unsigned char cmd = *writearr++;
writecnt--;
@@ -226,7 +242,7 @@ static int sb600_spi_send_command(const struct flashctx *flash, unsigned int wri
uint8_t readwrite = (readcnt + readoffby1) << 4 | (writecnt);
mmio_writeb(readwrite, sb600_spibar + 1);
- reset_internal_fifo_pointer();
+ reset_internal_fifo_pointer(sb600_spibar);
msg_pspew("Filling FIFO: ");
unsigned int count;
for (count = 0; count < writecnt; count++) {
@@ -234,16 +250,16 @@ static int sb600_spi_send_command(const struct flashctx *flash, unsigned int wri
mmio_writeb(writearr[count], sb600_spibar + 0xC);
}
msg_pspew("\n");
- if (compare_internal_fifo_pointer(writecnt))
+ if (compare_internal_fifo_pointer(writecnt, sb600_spibar))
return SPI_PROGRAMMER_ERROR;
/*
* We should send the data in sequence, which means we need to reset
* the FIFO pointer to the first byte we want to send.
*/
- reset_internal_fifo_pointer();
- execute_command();
- if (compare_internal_fifo_pointer(writecnt + readcnt))
+ reset_internal_fifo_pointer(sb600_spibar);
+ execute_command(sb600_spibar);
+ if (compare_internal_fifo_pointer(writecnt + readcnt, sb600_spibar))
return SPI_PROGRAMMER_ERROR;
/*
@@ -257,7 +273,7 @@ static int sb600_spi_send_command(const struct flashctx *flash, unsigned int wri
* the opcode, the FIFO already stores the response from the chip.
* Usually, the chip will respond with 0x00 or 0xff.
*/
- reset_internal_fifo_pointer();
+ reset_internal_fifo_pointer(sb600_spibar);
/* Skip the bytes we sent. */
msg_pspew("Skipping: ");
@@ -265,7 +281,7 @@ static int sb600_spi_send_command(const struct flashctx *flash, unsigned int wri
msg_pspew("[%02x]", mmio_readb(sb600_spibar + 0xC));
}
msg_pspew("\n");
- if (compare_internal_fifo_pointer(writecnt))
+ if (compare_internal_fifo_pointer(writecnt, sb600_spibar))
return SPI_PROGRAMMER_ERROR;
msg_pspew("Reading FIFO: ");
@@ -274,7 +290,7 @@ static int sb600_spi_send_command(const struct flashctx *flash, unsigned int wri
msg_pspew("[%02x]", readarr[count]);
}
msg_pspew("\n");
- if (compare_internal_fifo_pointer(writecnt+readcnt))
+ if (compare_internal_fifo_pointer(writecnt+readcnt, sb600_spibar))
return SPI_PROGRAMMER_ERROR;
if (mmio_readb(sb600_spibar + 1) != readwrite) {
@@ -292,11 +308,13 @@ static int spi100_spi_send_command(const struct flashctx *flash, unsigned int wr
const unsigned char *writearr,
unsigned char *readarr)
{
+ struct sb600spi_data *sb600_data = flash->mst->spi.data;
+ uint8_t *sb600_spibar = sb600_data->spibar;
/* First byte is cmd which can not be sent through the buffer. */
unsigned char cmd = *writearr++;
writecnt--;
msg_pspew("%s, cmd=0x%02x, writecnt=%d, readcnt=%d\n", __func__, cmd, writecnt, readcnt);
- mmio_writeb(cmd, sb600_spibar + 0);
+ mmio_writeb(cmd, sb600_spibar + SPI100_CMD_CODE_REG);
int ret = check_readwritecnt(flash, writecnt, readcnt);
if (ret != 0)
@@ -314,7 +332,7 @@ static int spi100_spi_send_command(const struct flashctx *flash, unsigned int wr
}
msg_pspew("\n");
- execute_command();
+ execute_spi100_command(sb600_spibar);
msg_pspew("Reading buffer: ");
for (count = 0; count < readcnt; count++) {
@@ -353,7 +371,7 @@ static const char* spireadmodes[] = {
"Fast Read",
};
-static int set_speed(struct pci_dev *dev, enum amd_chipset amd_gen, uint8_t speed)
+static int set_speed(struct pci_dev *dev, enum amd_chipset amd_gen, uint8_t speed, uint8_t *sb600_spibar)
{
bool success = false;
@@ -376,7 +394,7 @@ static int set_speed(struct pci_dev *dev, enum amd_chipset amd_gen, uint8_t spee
return 0;
}
-static int set_mode(struct pci_dev *dev, uint8_t mode)
+static int set_mode(struct pci_dev *dev, uint8_t mode, uint8_t *sb600_spibar)
{
msg_pdbg("Setting SPI read mode to %s (%i)... ", spireadmodes[mode], mode);
uint32_t tmp = mmio_readl(sb600_spibar + 0x00);
@@ -391,19 +409,19 @@ static int set_mode(struct pci_dev *dev, uint8_t mode)
return 0;
}
-static int handle_speed(struct pci_dev *dev, enum amd_chipset amd_gen)
+static int handle_speed(const struct programmer_cfg *cfg,
+ struct pci_dev *dev, enum amd_chipset amd_gen, uint8_t *sb600_spibar)
{
uint32_t tmp;
int16_t spispeed_idx = -1;
int16_t spireadmode_idx = -1;
- char *spispeed;
- char *spireadmode;
+ char *param_str;
- spispeed = extract_programmer_param("spispeed");
- if (spispeed != NULL) {
+ param_str = extract_programmer_param_str(cfg, "spispeed");
+ if (param_str != NULL) {
unsigned int i;
for (i = 0; i < ARRAY_SIZE(spispeeds); i++) {
- if (strcasecmp(spispeeds[i], spispeed) == 0) {
+ if (strcasecmp(spispeeds[i], param_str) == 0) {
spispeed_idx = i;
break;
}
@@ -412,36 +430,36 @@ static int handle_speed(struct pci_dev *dev, enum amd_chipset amd_gen)
* Error out on speeds not present in the spispeeds array.
* Only Yangtze supports the second half of indices.
* No 66 MHz before SB8xx. */
- if ((strcasecmp(spispeed, "reserved") == 0) ||
+ if ((strcasecmp(param_str, "reserved") == 0) ||
(i == ARRAY_SIZE(spispeeds)) ||
(amd_gen < CHIPSET_YANGTZE && spispeed_idx > 3) ||
(amd_gen < CHIPSET_SB89XX && spispeed_idx == 0)) {
- msg_perr("Error: Invalid spispeed value: '%s'.\n", spispeed);
- free(spispeed);
+ msg_perr("Error: Invalid spispeed value: '%s'.\n", param_str);
+ free(param_str);
return 1;
}
- free(spispeed);
+ free(param_str);
}
- spireadmode = extract_programmer_param("spireadmode");
- if (spireadmode != NULL) {
+ param_str = extract_programmer_param_str(cfg, "spireadmode");
+ if (param_str != NULL) {
unsigned int i;
for (i = 0; i < ARRAY_SIZE(spireadmodes); i++) {
- if (strcasecmp(spireadmodes[i], spireadmode) == 0) {
+ if (strcasecmp(spireadmodes[i], param_str) == 0) {
spireadmode_idx = i;
break;
}
}
- if ((strcasecmp(spireadmode, "reserved") == 0) ||
+ if ((strcasecmp(param_str, "reserved") == 0) ||
(i == ARRAY_SIZE(spireadmodes))) {
- msg_perr("Error: Invalid spireadmode value: '%s'.\n", spireadmode);
- free(spireadmode);
+ msg_perr("Error: Invalid spireadmode value: '%s'.\n", param_str);
+ free(param_str);
return 1;
}
if (amd_gen < CHIPSET_BOLTON) {
msg_perr("Warning: spireadmode not supported for this chipset.");
}
- free(spireadmode);
+ free(param_str);
}
/* See the chipset support matrix for SPI Base_Addr below for an explanation of the symbols used.
@@ -456,10 +474,10 @@ static int handle_speed(struct pci_dev *dev, enum amd_chipset amd_gen)
msg_pdbg("SPI read mode is %s (%i)\n",
spireadmodes[read_mode], read_mode);
if (spireadmode_idx < 0) {
- msg_perr("Warning: spireadmode not set, "
- "leaving spireadmode unchanged.");
+ msg_pdbg("spireadmode is not set, "
+ "leaving SPI read mode unchanged.\n");
}
- else if (set_mode(dev, spireadmode_idx) != 0) {
+ else if (set_mode(dev, spireadmode_idx, sb600_spibar) != 0) {
return 1;
}
@@ -499,33 +517,33 @@ static int handle_speed(struct pci_dev *dev, enum amd_chipset amd_gen)
}
}
if (spispeed_idx < 0) {
- msg_perr("Warning: spispeed not set, leaving spispeed unchanged.");
+ msg_pdbg("spispeed is not set, leaving SPI speed unchanged.\n");
return 0;
}
- return set_speed(dev, amd_gen, spispeed_idx);
+ return set_speed(dev, amd_gen, spispeed_idx, sb600_spibar);
}
-static int handle_imc(struct pci_dev *dev, enum amd_chipset amd_gen)
+static int handle_imc(const struct programmer_cfg *cfg, struct pci_dev *dev, enum amd_chipset amd_gen)
{
/* Handle IMC everywhere but sb600 which does not have one. */
if (amd_gen == CHIPSET_SB6XX)
return 0;
bool amd_imc_force = false;
- char *arg = extract_programmer_param("amd_imc_force");
- if (arg && !strcmp(arg, "yes")) {
+ char *param_value = extract_programmer_param_str(cfg, "amd_imc_force");
+ if (param_value && !strcmp(param_value, "yes")) {
amd_imc_force = true;
msg_pspew("amd_imc_force enabled.\n");
- } else if (arg && !strlen(arg)) {
+ } else if (param_value && !strlen(param_value)) {
msg_perr("Missing argument for amd_imc_force.\n");
- free(arg);
+ free(param_value);
return 1;
- } else if (arg) {
- msg_perr("Unknown argument for amd_imc_force: \"%s\" (not \"yes\").\n", arg);
- free(arg);
+ } else if (param_value) {
+ msg_perr("Unknown argument for amd_imc_force: \"%s\" (not \"yes\").\n", param_value);
+ free(param_value);
return 1;
}
- free(arg);
+ free(param_value);
/* TODO: we should not only look at IntegratedImcPresent (LPC Dev 20, Func 3, 40h) but also at
* IMCEnable(Strap) and Override EcEnable(Strap) (sb8xx, sb9xx?, a50, Bolton: Misc_Reg: 80h-87h;
@@ -537,7 +555,7 @@ static int handle_imc(struct pci_dev *dev, enum amd_chipset amd_gen)
}
if (!amd_imc_force)
- programmer_may_write = 0;
+ programmer_may_write = false;
msg_pinfo("Writes have been disabled for safety reasons because the presence of the IMC\n"
"was detected and it could interfere with accessing flash memory. Flashrom will\n"
"try to disable it temporarily but even then this might not be safe:\n"
@@ -566,55 +584,61 @@ static int promontory_read_memmapped(struct flashctx *flash, uint8_t *buf,
return 0;
}
-static struct spi_master spi_master_sb600 = {
- .max_data_read = FIFO_SIZE_OLD,
- .max_data_write = FIFO_SIZE_OLD - 3,
- .command = sb600_spi_send_command,
- .multicommand = default_spi_send_multicommand,
- .read = default_spi_read,
- .write_256 = default_spi_write_256,
- .write_aai = default_spi_write_aai,
-};
-
-static struct spi_master spi_master_yangtze = {
- .max_data_read = FIFO_SIZE_YANGTZE - 3, /* Apparently the big SPI 100 buffer is not a ring buffer. */
- .max_data_write = FIFO_SIZE_YANGTZE - 3,
- .command = spi100_spi_send_command,
- .multicommand = default_spi_send_multicommand,
- .read = default_spi_read,
- .write_256 = default_spi_write_256,
- .write_aai = default_spi_write_aai,
-};
-
-static struct spi_master spi_master_promontory = {
- .max_data_read = MAX_DATA_READ_UNLIMITED,
- .max_data_write = FIFO_SIZE_YANGTZE - 3,
- .command = spi100_spi_send_command,
- .multicommand = default_spi_send_multicommand,
- .read = promontory_read_memmapped,
- .write_256 = default_spi_write_256,
- .write_aai = default_spi_write_aai,
-};
-
static int sb600spi_shutdown(void *data)
{
- struct flashctx *flash = ((struct sb600spi_data *)data)->flash;
+ struct sb600spi_data *sb600_data = data;
+ struct flashctx *flash = sb600_data->flash;
if (flash)
finalize_flash_access(flash);
+
free(data);
return 0;
}
-int sb600_probe_spi(struct pci_dev *dev)
+static const struct spi_master spi_master_sb600 = {
+ .max_data_read = FIFO_SIZE_OLD,
+ .max_data_write = FIFO_SIZE_OLD - 3,
+ .command = sb600_spi_send_command,
+ .map_flash_region = physmap,
+ .unmap_flash_region = physunmap,
+ .read = default_spi_read,
+ .write_256 = default_spi_write_256,
+ .shutdown = sb600spi_shutdown,
+};
+
+static const struct spi_master spi_master_yangtze = {
+ .max_data_read = FIFO_SIZE_YANGTZE - 3, /* Apparently the big SPI 100 buffer is not a ring buffer. */
+ .max_data_write = FIFO_SIZE_YANGTZE - 3,
+ .command = spi100_spi_send_command,
+ .map_flash_region = physmap,
+ .unmap_flash_region = physunmap,
+ .read = default_spi_read,
+ .write_256 = default_spi_write_256,
+ .shutdown = sb600spi_shutdown,
+};
+
+static const struct spi_master spi_master_promontory = {
+ .max_data_read = MAX_DATA_READ_UNLIMITED,
+ .max_data_write = FIFO_SIZE_YANGTZE - 3,
+ .command = spi100_spi_send_command,
+ .map_flash_region = physmap,
+ .unmap_flash_region = physunmap,
+ .read = promontory_read_memmapped,
+ .write_256 = default_spi_write_256,
+ .shutdown = sb600spi_shutdown,
+};
+
+int sb600_probe_spi(const struct programmer_cfg *cfg, struct pci_dev *dev)
{
struct pci_dev *smbus_dev;
uint32_t tmp;
uint8_t reg;
+ uint8_t *sb600_spibar = NULL;
/* Read SPI_BaseAddr */
tmp = pci_read_long(dev, 0xa0);
tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */
- msg_pdbg("SPI base address is at 0x%x\n", tmp);
+ msg_pdbg("SPI base address is at 0x%"PRIx32"\n", tmp);
/* If the BAR has address 0, it is unlikely SPI is used. */
if (!tmp)
@@ -623,7 +647,7 @@ int sb600_probe_spi(struct pci_dev *dev)
/* Physical memory has to be mapped at page (4k) boundaries. */
sb600_spibar = rphysmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000);
if (sb600_spibar == ERROR_PTR)
- return ERROR_FATAL;
+ return ERROR_FLASHROM_FATAL;
/* The low bits of the SPI base address are used as offset into
* the mapped page.
@@ -632,7 +656,7 @@ int sb600_probe_spi(struct pci_dev *dev)
enum amd_chipset amd_gen = determine_generation(dev);
if (amd_gen == CHIPSET_AMD_UNKNOWN)
- return ERROR_NONFATAL;
+ return ERROR_FLASHROM_NONFATAL;
/* How to read the following table and similar ones in this file:
* "?" means we have no datasheet for this chipset generation or it doesn't have any relevant info.
@@ -652,14 +676,14 @@ int sb600_probe_spi(struct pci_dev *dev)
*/
if (amd_gen >= CHIPSET_SB7XX) {
tmp = pci_read_long(dev, 0xa0);
- msg_pdbg("SpiRomEnable=%i", (tmp >> 1) & 0x1);
+ msg_pdbg("SpiRomEnable=%"PRIi32"", (tmp >> 1) & 0x1);
if (amd_gen == CHIPSET_SB7XX)
- msg_pdbg(", AltSpiCSEnable=%i, AbortEnable=%i", tmp & 0x1, (tmp >> 2) & 0x1);
+ msg_pdbg(", AltSpiCSEnable=%"PRIi32", AbortEnable=%"PRIi32"", tmp & 0x1, (tmp >> 2) & 0x1);
else if (amd_gen >= CHIPSET_YANGTZE)
- msg_pdbg(", RouteTpm2Sp=%i", (tmp >> 3) & 0x1);
+ msg_pdbg(", RouteTpm2Sp=%"PRIi32"", (tmp >> 3) & 0x1);
tmp = pci_read_byte(dev, 0xba);
- msg_pdbg(", PrefetchEnSPIFromIMC=%i", (tmp & 0x4) >> 2);
+ msg_pdbg(", PrefetchEnSPIFromIMC=%"PRIi32"", (tmp & 0x4) >> 2);
tmp = pci_read_byte(dev, 0xbb);
/* FIXME: Set bit 3,6,7 if not already set.
@@ -667,8 +691,8 @@ int sb600_probe_spi(struct pci_dev *dev)
* See doc 42413 AMD SB700/710/750 RPR.
*/
if (amd_gen == CHIPSET_SB7XX)
- msg_pdbg(", SpiOpEnInLpcMode=%i", (tmp >> 5) & 0x1);
- msg_pdbg(", PrefetchEnSPIFromHost=%i\n", tmp & 0x1);
+ msg_pdbg(", SpiOpEnInLpcMode=%"PRIi32"", (tmp >> 5) & 0x1);
+ msg_pdbg(", PrefetchEnSPIFromHost=%"PRIi32"\n", tmp & 0x1);
}
/* Chipset support matrix for SPI_Cntrl0 (spibar + 0x0)
@@ -690,49 +714,49 @@ int sb600_probe_spi(struct pci_dev *dev)
* <1> see handle_speed
*/
tmp = mmio_readl(sb600_spibar + 0x00);
- msg_pdbg("(0x%08" PRIx32 ") SpiArbEnable=%i", tmp, (tmp >> 19) & 0x1);
+ msg_pdbg("(0x%08" PRIx32 ") SpiArbEnable=%"PRIi32"", tmp, (tmp >> 19) & 0x1);
if (amd_gen >= CHIPSET_YANGTZE)
- msg_pdbg(", IllegalAccess=%i", (tmp >> 21) & 0x1);
+ msg_pdbg(", IllegalAccess=%"PRIi32"", (tmp >> 21) & 0x1);
- msg_pdbg(", SpiAccessMacRomEn=%i, SpiHostAccessRomEn=%i, ArbWaitCount=%i",
+ msg_pdbg(", SpiAccessMacRomEn=%"PRIi32", SpiHostAccessRomEn=%"PRIi32", ArbWaitCount=%"PRIi32"",
(tmp >> 22) & 0x1, (tmp >> 23) & 0x1, (tmp >> 24) & 0x7);
if (amd_gen < CHIPSET_YANGTZE)
- msg_pdbg(", SpiBridgeDisable=%i", (tmp >> 27) & 0x1);
+ msg_pdbg(", SpiBridgeDisable=%"PRIi32"", (tmp >> 27) & 0x1);
switch (amd_gen) {
case CHIPSET_SB7XX:
- msg_pdbg(", DropOneClkOnRd/SpiClkGate=%i", (tmp >> 28) & 0x1);
+ msg_pdbg(", DropOneClkOnRd/SpiClkGate=%"PRIi32"", (tmp >> 28) & 0x1);
/* Fall through. */
case CHIPSET_SB89XX:
case CHIPSET_HUDSON234:
case CHIPSET_YANGTZE:
case CHIPSET_PROMONTORY:
- msg_pdbg(", SpiBusy=%i", (tmp >> 31) & 0x1);
+ msg_pdbg(", SpiBusy=%"PRIi32"", (tmp >> 31) & 0x1);
default: break;
}
msg_pdbg("\n");
if (((tmp >> 22) & 0x1) == 0 || ((tmp >> 23) & 0x1) == 0) {
msg_perr("ERROR: State of SpiAccessMacRomEn or SpiHostAccessRomEn prohibits full access.\n");
- return ERROR_NONFATAL;
+ return ERROR_FLASHROM_NONFATAL;
}
if (amd_gen >= CHIPSET_SB89XX) {
tmp = mmio_readb(sb600_spibar + 0x1D);
- msg_pdbg("Using SPI_CS%d\n", tmp & 0x3);
+ msg_pdbg("Using SPI_CS%"PRId32"\n", tmp & 0x3);
/* FIXME: Handle SpiProtect* configuration on Yangtze. */
}
/* Look for the SMBus device. */
- smbus_dev = pci_dev_find(0x1002, 0x4385);
+ smbus_dev = pcidev_find(0x1002, 0x4385);
if (!smbus_dev)
- smbus_dev = pci_dev_find(0x1022, 0x780b); /* AMD FCH */
+ smbus_dev = pcidev_find(0x1022, 0x780b); /* AMD FCH */
if (!smbus_dev)
- smbus_dev = pci_dev_find(0x1022, 0x790b); /* AMD FP4 */
+ smbus_dev = pcidev_find(0x1022, 0x790b); /* AMD FP4 */
if (!smbus_dev) {
msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n");
- return ERROR_NONFATAL;
+ return ERROR_FLASHROM_NONFATAL;
}
/* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */
@@ -764,35 +788,28 @@ int sb600_probe_spi(struct pci_dev *dev)
return 0;
}
- if (handle_speed(dev, amd_gen) != 0)
- return ERROR_FATAL;
+ if (handle_speed(cfg, dev, amd_gen, sb600_spibar) != 0)
+ return ERROR_FLASHROM_FATAL;
- if (handle_imc(dev, amd_gen) != 0)
- return ERROR_FATAL;
+ if (handle_imc(cfg, dev, amd_gen) != 0)
+ return ERROR_FLASHROM_FATAL;
- struct sb600spi_data *data = calloc(1, sizeof(struct sb600spi_data));
+ struct sb600spi_data *data = calloc(1, sizeof(*data));
if (!data) {
msg_perr("Unable to allocate space for extra SPI master data.\n");
return SPI_GENERIC_ERROR;
}
data->flash = NULL;
-
- register_shutdown(sb600spi_shutdown, data);
- spi_master_sb600.data = data;
- spi_master_yangtze.data = data;
- spi_master_promontory.data = data;
-
+ data->spibar = sb600_spibar;
/* Starting with Yangtze the SPI controller got a different interface with a much bigger buffer. */
if (amd_gen < CHIPSET_YANGTZE)
- register_spi_master(&spi_master_sb600);
+ register_spi_master(&spi_master_sb600, data);
else if (amd_gen == CHIPSET_YANGTZE)
- register_spi_master(&spi_master_yangtze);
+ register_spi_master(&spi_master_yangtze, data);
else
- register_spi_master(&spi_master_promontory);
+ register_spi_master(&spi_master_promontory, data);
return 0;
}
-
-#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-03 18:41:02 +0000