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* ch341a_spi: drop validation of handle in routinesAlexander Goncharov2023-04-131-10/+0
| | | | | | | | | | | | | Since the handle is no longer a global variable and only exists during the lifetime of the driver, we can stop checking if the handle equals NULL. Change-Id: I1872495b83a522ceced331fef35d9d9d3b43fce5 Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72808 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* ch341a_spi: Refactor singleton states into reentrant patternAlexander Goncharov2023-04-131-75/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move global singleton states into a struct and store within the spi_master data field for the life-time of the driver. This patchset also includes stdlib.h to be able to work with memory allocation. Pass programmer's data as a parameter to functions that need it. This is one of the steps on the way to move spi_master data memory management behind the initialisation API, for more context see other patches under the same topic specified below. TOPIC=register_master_api TEST=Tested on flash W25Q128JVSQ flashrom -E # Result: success flashrom -v ff.bin # Result: verified flashrom -w firmware.bin # Result: success flashrom -v firmware.bin # Result: verified Change-Id: I9fe72bff88b7f8778c1199bdab8ba43bf32e1c8c Signed-off-by: Alexander Goncharov <chat@joursoir.net> Ticket: https://ticket.coreboot.org/issues/391 Reviewed-on: https://review.coreboot.org/c/flashrom/+/72807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* cli_classic: refactor arguments parsing into separate funcAlexander Goncharov2023-04-131-245/+270
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move variables that represent parsed options to `cli_options` structure. This patchset also introduces the following functions: - parse_options() which parses command line arguments and fills the structure. - free_options() that releases an allocated data from the structure. This is one of the steps on the way to simplify the main function by using helper functions with descriptive names. TOPIC=split_main_func TEST=the following scenarious run successfully ./flashrom -p dummy:emulate=S25FL128L -V ./flashrom -p dummy:size=8388608,emulate=VARIABLE_SIZE \ -r /tmp/dump.rom ./flashrom -p dummy:emulate=W25Q128FV -l /tmp/rom.layout \ -i boot -w /tmp/rom.tr.img ./flashrom -p dummy:emulate=W25Q128FV --wp-list ./flashrom -p dummy:emulate=W25Q128FV,hwwp=yes \ --wp-enable \ --wp-range=0x00c00000,0x00400000 \ --wp-status $ head -c 16MiB </dev/urandom >/tmp/image.rom ./flashrom -p dummy:image=/tmp/image.rom,emulate=S25FL128L \ -c S25FL128L -E -V Change-Id: Id573bc74e3bb46b7dc42f1452fff6394d4f091bc Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* usb_device.c: detach/attach usb kernel driver explicitlyThomas Heijligen2023-04-121-3/+9
| | | | | | | | | | | | | | | | Use `libusb_detach_kernel_driver` and `libusb_attach_kernel_driver` instead of `libusb_auto_detach_kernel_driver` to be compatible with older libusb versions without changing the behavior. TEST=Build with libusb >= 1.0.9 Change-Id: I1363fea13368b7ac1e9a3829864d06d123c4e157 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67073 Reviewed-by: Peter Marheine <pmarheine@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* MAINTAINERS: Remove Felix SingerFelix Singer2023-04-061-11/+0
| | | | | | | | | | | | | I haven't worked on flashrom in the last months and I'm also not planning to continue working on it again. So I'm removing myself from the maintainers file since I'm not maintaining anymore. Items, which become unmaintained, are removed. Change-Id: I33903c4e38a24e6bf3cb233d28b297d1fa3716a9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/74274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/: Case write_granularity enum valuesEdward O'Callaghan2023-04-065-41/+41
| | | | | | | | Change-Id: Ic8c655225abe477c1b618dc685b743e691c16ebd Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/74165 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* internal: Move laptop_ok into board_cfgEdward O'Callaghan2023-04-065-44/+45
| | | | | | | | | | | | | | | | | | | | | | Due to how internal is structured around chipset_flash_enable() entry we need to prepare a crafted programmer_cfg that contains a board_enable substructure with data derived from the board_enable subsystem. While this is certainly not perfection, it does make clear the relationships between board_enable into chipset_flash_enable and subsequently the overall internal programmer initialisation in a RAII fashion at the type level over closure upon global state that is impossible to reason about. Also flip predicate in report_nonwl_laptop_detected() and return early with the trivial base-case. TEST=`$ sudo ./flashrom -p internal --flash-name`. Change-Id: I459215253845c2af73262943ce91a36464e9eb06 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* internal: Move is_laptop into board_cfgEdward O'Callaghan2023-04-023-9/+8
| | | | | | | | Change-Id: I24e38e4457299934acdcd70325d0bf0f4b139e5f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73455 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* board_enables: Allow for prog cfg coupling with board cfgEdward O'Callaghan2023-04-024-89/+96
| | | | | | | | | | | | | | Some boards need to configure the programmer in specific ways. For example, a programmer such as internal may need to be configured either as laptop or not type and as such the board enable needs the ability to feed state back into the programmer configuration. Plumb this though by creating a board_cfg structure that can be packed. Change-Id: I7058a693e714a6966a842ae97cc8da7296e63e5e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71623 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* board_enable.c: Consistent board_flash_enable() nullarity checksEdward O'Callaghan2023-03-281-4/+4
| | | | | | | | | | | | Use a consistent style, as is the case in the Linux kernel, of the canonical form of nullarity checking. Thus, making the function have a overall consistent style. Change-Id: Id28b8b70d9ecc9f69a1b61684500d9c6023ca045 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73454 Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* board_enable.c: Clean up board_handle_phase()Edward O'Callaghan2023-03-281-6/+1
| | | | | | | | | | | The board_enable_safetycheck() call already checks nullarity of the function pointer. Change-Id: I956961ee7204d3a6a9066ba5945f95af1411e700 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73453 Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* dmi.c: Pass is_laptop by ref into dmiEdward O'Callaghan2023-03-284-31/+31
| | | | | | | | | | | Prefix the remaining global cases with `g_` to avoid shadowing issues and for easy greping. Change-Id: I3d5ad6c0623269492d775a99a947fd6fe26c5f91 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* tree/: Rename 'laptop_ok-> g_laptop_ok' to avoid shadowingEdward O'Callaghan2023-03-284-12/+12
| | | | | | | | | | Avoid global symbol shadowing in local functions. Change-Id: Idfca0b7e46d8051bf680227250cf40483e19dc53 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* flashchips: Add Macronix MX25V1635F supportPoroCYon2023-03-262-0/+36
| | | | | | | | | | | | | | | See https://www.mxic.com.tw/Lists/Datasheet/Attachments/8662/MX25V1635F,%202.5V,%2016Mb,%20v1.4.pdf . I've tested this patch with the MX25V1635F I have here, using serprog and ftdi by (re)writing a few images to the flash and seeing if changes were stored correctly. This also included erasing and rewriting the memory with completely different data, so erase is tested, too. Change-Id: I58ddaaa96ef410d50dde3aaa20376c5bbf0f370b Signed-off-by: PoroCYon <p@pcy.be> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips: Add Macronix MX25V8035F supportPoroCYon2023-03-262-0/+36
| | | | | | | | | | | | | | | See https://www.macronix.com/Lists/Datasheet/Attachments/8405/MX25V8035F,%202.5V,%208Mb,%20v1.0.pdf . I've only tested this patch with the MX25V1635F I have here, though other chips in the series exist as well. Tested using serprog and ftdi by writing a few images to the flash and seeing if changes were stored correctly. Change-Id: Ic5be2da4cfa2a2ff044a519bb6f367f21c15e4b8 Signed-off-by: PoroCYon <p@pcy.be> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips: Add Macronix MX25V4035F supportPoroCYon2023-03-262-0/+37
| | | | | | | | | | | | | | | See https://www.macronix.com/Lists/Datasheet/Attachments/8670/MX25V4035F,%202.5V,%204Mb,%20v1.2.pdf . I've only tested this patch with the MX25V1635F I have here, though other chips in the series exist as well. Tested using serprog and ftdi by writing a few images to the flash and seeing if changes were stored correctly. Change-Id: I8b26926c354b840ca7b14b4c5cb000e3c02f5137 Signed-off-by: PoroCYon <p@pcy.be> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* MAINTAINERS: Re-order programmer entries alphabeticallyAnastasia Klimchuk2023-03-241-5/+5
| | | | | | | | | Change-Id: I7e9013fd4cd3b9ea6ecdb45fabbc3c57c4076a17 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73965 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Miklós Márton <martonmiklosqdev@gmail.com>
* tree/: Convert printlock func ptr into enumerate valuesEdward O'Callaghan2023-03-224-97/+135
| | | | | | | | | | | | | | | | | | | Converting the printlock function pointer within the flashchip struct into enum values allows for the flashchips db to be turn into pure, declarative data. A nice side-effect of this is to reduce link-time symbol space of chipdrivers and increase modularity of the spi25_statusreg.c and related implementations. BUG=none TEST=ninja test. Change-Id: I9131348f72c1010e2c213dca4dc4b675a8d8681e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
* Revert "pcidev: remove pcidev_getdevfn() function"Thomas Heijligen2023-03-203-2/+10
| | | | | | | | | | | | | | | As Edward pointed out correctly this function does more than abstracting the different versions of `pci_get_dev()`. It also hide the usage of the global `struct pci_access pacc` from the caller. This reverts commit 0e8902f1ff2b927bb91a5e89e4fde3d8d71f6692. Change-Id: I0cd2f54cb6a6e35dc353476e0f5e502cbbd06cba Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tree/: Convert unlock func ptr into enumerate valuesEdward O'Callaghan2023-03-208-74/+130
| | | | | | | | | | | | | | | | | | | Converting the blockprotect unlock function pointer within the flashchip struct into enum values allows for the flashchips db to be turn into pure, declarative data. A nice side-effect of this is to reduce link-time symbol space of chipdrivers and increase modularity of the spi25_statusreg.c and related implementations. BUG=none TEST=ninja test. Change-Id: Ie5c5db1b09d07e1a549990d6f5a622fae4c83233 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tests: Add wrap for __fstat50 to fix tests for NetBSDAnastasia Klimchuk2023-03-163-0/+8
| | | | | | | | | | | | | | Tested by running unit tests on NetBSD 9.2 Ubuntu 22.04.1 (still pass) Change-Id: Icb8e453328cb40ab9d628f01ecdc3886a233dad5 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* MAINTAINERS: Add Nikolai Artemiev for raiden_debug_spiNikolai Artemiev2023-03-141-0/+5
| | | | | | | | | | | | | | BUG=none BRANCH=none TEST=none Change-Id: Ie70eafb301b3363caa8e670b67a16cd25c7e15a8 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* MAINTAINERS: Add Aarya Chaumal for erasure_layoutAarya Chaumal2023-03-141-0/+6
| | | | | | | | | Change-Id: Id0188add883336f2fb494e4169a668e8b502682f Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* fmap: ignore areas with zero sizePeter Marheine2023-03-141-0/+10
| | | | | | | | | | | | | | | | | | | | | | | It's impossible for flashrom_layout to represent zero-sized flash regions but it is possible for a fmap to contain a zero-sized region which causes the resulting layout to fail layout_sanity_checks(), preventing use of that fmap. Because it would very rarely make sense to be able to operate on zero-sized regions anyway and changing layouts to be able to support zero-size regions would entail large changes, instead ignore zero-size regions when present in fmap. TEST=Warning is now printed when using fmap that contains a zero-sized area, and operations on other regions are allowed to proceed. BUG=b:271933192 Change-Id: Ie20971f779acece7a0b3b8f38796fff128ce689a Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* pcidev: remove pcidev_getdevfn() functionThomas Heijligen2023-03-103-10/+2
| | | | | | | | | | | This function is only called once. Move the content of the function into the caller. Change-Id: Id2983420080f75ae6992edfb032bf5c83b29c803 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* libpci: drop support for pciutils < 2.2.0Thomas Heijligen2023-03-105-40/+16
| | | | | | | | | | | | | | This version was released in september 2005 and had a breaking api change. Drop it so that we don't need to maintain the old codepath any longer. Beside that, we have already a second codepath which is using the new `pci_get_dev` variant exclusively. Change-Id: If943db350b561a005d8292a53d9255223db3d571 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* include/pci.h: Use __has_include() macro to test pci.h pathThomas Heijligen2023-03-101-3/+7
| | | | | | | | | | | | | | | Some NetBSDs have the pci.h under pciutils/ instead of pci/. But we can't say for sure which variants uses which include path. Just test them with the __has_include() compiler macro. https://gcc.gnu.org/onlinedocs/cpp/_005f_005fhas_005finclude.html Change-Id: Ib20de6bffede910b89937f554b4d56f4799f0762 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73292 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* MAINTAINERS: Add Jean THOMAS for DirtyJTAGJean THOMAS2023-03-101-0/+5
| | | | | | | | | Signed-off-by: Jean THOMAS <virgule@jeanthomas.me> Change-Id: I0d45b9c634dd6f7509e366723e7fe727f0d087cd Reviewed-on: https://review.coreboot.org/c/flashrom/+/73552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips: Mark AM29LV040B as write-testedAnastasia Klimchuk2023-03-061-1/+1
| | | | | | | | | | | | | Reported by Alex Perez on the mailing list, write operation done successfully with satasii programmer. https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/67OX4CSBGWAGMNGEOATBJGFJCKFD64SU/ Change-Id: I8a42f8214b09c455a10a1f1e9e69feaeca2c62a1 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashchips: Mark XMC XM25QH64C as TEST_OK_PREWThomas Heijligen2023-03-061-1/+1
| | | | | | | | | | | | | As reported on the mailing list[0] this flashchip was successfully probed, read, erased and written with a ch341a programmer. [0] https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/message/SMIHEXHZBSCGE2Y2EG75XQHWSKEQ3PP6 Change-Id: Ifca84d9a44bb20091293356f5b1643de41220b64 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips: Mark XMC XM25QH256C as TEST_OK_PRThomas Heijligen2023-03-061-1/+1
| | | | | | | | | | | | | As reported on the mailing list[0] this flashchip was successfully probed and read with a ch341a programmer. [0] https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/message/BFBKAJKURZHYQ6OTV3UAA7V5O2ZSJWGN Change-Id: I68d0315f7b29f27ac84374ea7cc69dca207bbacb Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* meson: fix typo "documtation" -> "documentation"Thomas Heijligen2023-03-031-1/+1
| | | | | | | | | | | | When building with -Ddocumentation=enabled/disabled this typo terminates meson because meson can't find the misspellt option. Change-Id: Ia4205b89fd0d7e77ecbcd29392187d8911dd1049 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* meson: revert to meson version 0.53.0Thomas Heijligen2023-03-033-6/+3
| | | | | | | | | | | | | | | | Debian Bullseye, current stable release, ships only with meson 0.56.2. To go back to an older meson version pass the project_version info as parameter to `sphinx-build` instead of using an environment variable. This is done by overriding the `release` variable in conf.py with `-Drelease=meson.project_version()` at the command line call. Change-Id: Iff9b8307c741a247a652cf666935c9485fa493fa Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Goncharov <chat@joursoir.net> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tree/: Drop default_spi_probe_opcode for NULL caseEdward O'Callaghan2023-03-0329-35/+10
| | | | | | | | | | | | | | | | | | | A NULL func pointer is necessary and sufficient for the condition `NULL func pointer => true' as to not need this boilerplate as it implies default behaviour of a supported opcode within the `check_block_eraser()` match supported loop. Ran; ``` $ find . -name '*.[c,h]' -exec sed -i '/.probe_opcode = default_spi_probe_opcode,/d' '{}' \; ``` Change-Id: Id502c5d2596ad1db52faf05723083620e4c52c12 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* spi: Make default cmd helpers static internalEdward O'Callaghan2023-03-032-23/+19
| | | | | | | | | | | | | | | | | | | | Avoid these leaking into driver implementations as a NULL field now implies their implementation. This removes one source of a driver bug where both `mst->command` AND `mst->multicommand` are set to default implementations which is actually a cyclical control flow condition. The driver however must still have either `mst->command` OR `mst->multicommand` defined and so both cannot be NULL. This simplifies the code and driver development. Change-Id: I4ef95846c2f005cf4aa727f31548c6877d2d4801 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* writeprotect: Add function to get register values and WP bit masksNikolai Artemiev2023-03-035-0/+101
| | | | | | | | | | | | | | | | | | | | | | | Add a new wp_cfg_to_reg_values() function that takes a generic wp_cfg instance and returns the chip-specific values that need to be written to the chip's registers to enable the specified protection range/mode. The function returns three values for each chip register: - reg_values[reg] - Value writeprotect will write to reg - bit_masks[reg] - Bit mask for WP-related bits in reg - write_masks[reg] - Bit mask for writable WP-related bits in reg (i.e. the ones writeprotect will try to write) BUG=b:260019525,b:259013033,260020006 BRANCH=none TEST=ninja test Change-Id: Ib2a47153b230c9f82bb4eca357c335f2abbacc20 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69847 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
* dummyflasher: Add basic WP support for opaque VARIABLE_SIZE chipNikolai Artemiev2023-03-021-0/+30
| | | | | | | | | | | | | | | | | | | | | | | Since VARIABLE_SIZE emulated chips do not correspond to actual flash chip models, no active protection modes are supported: - read_wp_cfg always returns mode=disabled,range=0,0 - write_wp_cfg only accepts mode=disabled,range=0,0 However this is sufficient to support use cases where the user just needs to verify that write protection is not enabled, as is the case in some futility unit tests. BUG=b:238694831,b:260531154 BRANCH=none TEST=none Change-Id: I4348e0175b8c743365904f5e61fdb69e3f4f4db5 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73289 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi: Make 'default_spi_send_multicommand' the default unless definedEdward O'Callaghan2023-03-0125-30/+5
| | | | | | | | | | | | | | | | | | | A NULL func pointer is necessary and sufficient for the condition `NULL func pointer => default_spi_send_multicommand' as to not need this explicit specification of 'default'. Therefore drop the explicit need to specify the 'default_spi_send_multicommand' callback function pointer in the spi_master struct. This is a reasonable default for every other driver in the tree with only a few exceptions. This simplifies the code and driver development. Change-Id: I6cc24bf982da3d5251d391eb397db43dd10280e8 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* doc/classic_cli_manpage: add missing chip for ft2232_spi programmerAlexander Goncharov2023-03-011-1/+1
| | | | | | | | | | | FTDI FT4233H chip was added in commit bc2e3b6b79dd1383cdf3d965df2fc5c0d6596b02 Change-Id: Id25f6444bfe871f7b01ae2caff23ce973b44567a Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* move manpage to sphinxThomas Heijligen2023-03-019-1870/+1468
| | | | | | | | | | | | | | | | | | | | | | | | | Use sphinx (sphinx-doc.org) to generate the UNIX man page from an reStructuredText file instead of dealing with plain groff. Use `meson setup -Dman-pages=enabled` to build the man page, and `meson setup -Ddocumentation=enabled` to build the web documentation explicitly. Both are enabled automatically if sphinx-build is found. The man page will be installed as `<meson_mandir>/man8/flashrom.8` and The html documentation in <meson_datadir>/doc/flashrom/html`. The Makefile builds only the man-page format. Increase the minimum version of meson from 0.53.0 to 0.57.0 to be able to pass environment variables to the custom_target() command. That is needed to pass the FLASHROM_VERSION to the documentation. Change-Id: Iee9f1164c5913e47385e6f7d51dc7775a58b5a67 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Alexander Goncharov <chat@joursoir.net>
* spi: Make 'default_spi_send_command' the default unless definedEdward O'Callaghan2023-02-272-5/+5
| | | | | | | | | | | | | | | | | A NULL func pointer is necessary and sufficient for the condition `NULL func pointer => default_spi_send_command' as to not need this explicit specification of 'default'. Therefore drop the explicit need to specify the 'default_spi_send_command' callback function pointer in the spi_master struct. This is a reasonable default for every other driver in the tree with only a few exceptions. This simplifies the code and driver development. Change-Id: I63abcb8c64f233cdbf58a149a31051fa648305a2 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* jedec.c: Provide better lexical scope to itermediatesEdward O'Callaghan2023-02-271-10/+6
| | | | | | | | | Change-Id: I8e01d471bb33a933b80760df2c69a4bf3589ba76 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* jedec.c: Tidy up whitespace and line wrapsEdward O'Callaghan2023-02-271-7/+6
| | | | | | | | | Change-Id: I3f18609709e59cdfc5a853c6e1ae5f53aecacc1a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* jedec.c: Add a little more const correctnessEdward O'Callaghan2023-02-271-5/+4
| | | | | | | | | Change-Id: Ic9a76ce3734bd83399c95478a7c0bfc081211124 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* jedec.c: Rename func to jedec_write_page()Edward O'Callaghan2023-02-271-2/+2
| | | | | | | | | Change-Id: I1be83d5974e305bddceaa34b64e982b774ade0d2 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* jedec.c: Drop branching non-zero programmer_delay() operandsEdward O'Callaghan2023-02-271-10/+5
| | | | | | | | | | | | | The programmer_delay() function is already tolerant upon zero delay values and will simply just return with a NOP. Therefore there is no need to branch. Change-Id: Ic547669bb16e6ace4fe283e07345fc2d7075d63e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* ch347_spi: Add initial support for the WCH CH347Nicholas Chin2023-02-279-10/+386
| | | | | | | | | | | | | | | | | | | | | | | Add support for the WCH CH347, a high-speed USB to bus converter supporting multiple protocols interfaces including SPI. Currently only mode 1 (vendor defined communication interface) is supported, mode 2 (USB HID communication interface) support will be added later. The code is currently hard coded to use CS1 and a SPI clock of 15 MHz, though there are 2 CS lines and 6 other GPIO lines available, as well as a configurable clock divisor for up to 60MHz operation. Support for these will be exposed through programmer parameters in later commits. This currently uses the synchronous libusb API. Performance seems to be alright so far, if it becomes an issue I may switch to the asynchronous API. Tested with a MX25L1606E flash chip Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Change-Id: I31b86c41076cc45d4a416a73fa1131350fb745ba Reviewed-on: https://review.coreboot.org/c/flashrom/+/70573 Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* asm106x: add programmer for ASM106x SATA controllersAlex Badea2023-02-278-9/+190
| | | | | | | | | | | | | | | | | | | | The ASMedia ASM106x series is a PCIe-SATA controller chip. It supports an attached SPI flash chip that can contain configuration and PCI option ROM. The interface is a simple shifter accessed via PCI config space, up to 4 bytes at a time. Add a programmer driver for it. Tested on a G536PCE1061V11 IO-PCE1061-V1.1 PCIe card, and a MPCE2ST-A01 VER006S mini-PCIe card, both with chips marked ASM1061, both enumerate as: 01:00.0 SATA controller [0106]: ASMedia Technology Inc. ASM1062 Serial ATA Controller [1b21:0612] (rev 02) (prog-if 01 [AHCI 1.0]) Subsystem: ASMedia Technology Inc. ASM1062 Serial ATA Controller [1b21:1060] Change-Id: I591b117be911bdb8249247c20530c1cf70f6e70d Signed-off-by: Alex Badea <vamposdecampos@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* MAINTAINERS: Update unit tests from Supported to MaintainedAnastasia Klimchuk2023-02-271-1/+1
| | | | | | | | Change-Id: I13853c6c48eb4054d2ed7d79bcfc768684914797 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73277 Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* MAINTAINERS: flashrom_tester: Change emailEvan Benn2023-02-261-1/+1
| | | | | | | | | | Change-Id: Ic1a53ddbc38e7d63f7b15aa2b31c63a5b65746f9 Signed-off-by: Evan Benn <evanbenn@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-19 16:23:57 +0000