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* flashchips.c: Make .tested lines consistentAlan Green2019-07-051-2/+2
| | | | | | | | | | | | | As per comments on https://review.coreboot.org/c/flashrom/+/33833/, make placement of spaces in .tested attributes with literal definitions consistent. Signed-off-by: Alan Green <avg@google.com> Change-Id: I18118f9f1e858547170fda8412bf6769f5cdcf53 Reviewed-on: https://review.coreboot.org/c/flashrom/+/33998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips.c: Sort file by vendor and modelAlan Green2019-07-051-4145/+4148
| | | | | | | | | | | | | | | For self-consistency, and to allow tools to assist with merging the chromium fork of flashrom, sort the entries of flashchips.c. The file is already largely sorted, though deviations have crept in over time. This is a non-clever mostly ASCII-order sorting. It is not intended to be permanent. Change-Id: I75a99583592526f60ba5264e92391bf8b1213b20 Reviewed-on: https://review.coreboot.org/c/flashrom/+/33931 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: Format SFDP-capable chip entryAlan Green2019-07-041-9/+8
| | | | | | | | | | | | | | | | To allow automated tools to manipulate flashchips.c, make the definition of SFDP-capable chip more consistent with other definitions. This involves - reordering fields to match both other entries and the definition of struct flashchip. - reformatting comments to make them consistent with other entries. Signed-off-by: Alan Green <avg@google.com> Change-Id: I8708a11993822085b3e8d8c80532dfb935d39876 Reviewed-on: https://review.coreboot.org/c/flashrom/+/33834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips.c: Make comment placement consistentAlan Green2019-07-041-1/+2
| | | | | | | | | | | | For consistency, move a comment about an entry from inside the open brace to outside it. Signed-off-by: Alan Green <avg@google.com> Change-Id: Ie9a745b7e7dc752cfd6fc14ebeb04754179893c6 Reviewed-on: https://review.coreboot.org/c/flashrom/+/33837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips.c: Fix field orderAlan Green2019-07-041-15/+15
| | | | | | | | | | | | | For consistency and in order to allow automated tools to work with flashchips.c, put fields in the same order as they are defined in struct flashchip, in flash.h Signed-off-by: Alan Green <avg@google.com> Change-Id: I5e0d81cb71b2c50ffeb9bb70267f16e9ac7a263c Reviewed-on: https://review.coreboot.org/c/flashrom/+/33833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashchips.c: Add comma after every .voltage attributeAlan Green2019-07-041-2/+2
| | | | | | | | | | | | | | To allow automated tools to manipulate flashchips.c, ensure that every voltage attribute ends with a comma, even if it is the last member in the definition. Signed-off-by: Alan Green <avg@google.com> Change-Id: Ie609d11ab846361f375f7b024d6ca55f83b01682 Reviewed-on: https://review.coreboot.org/c/flashrom/+/33832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* flashchips: Drop dead code of AT26DF321Alan Green2019-07-041-19/+1
| | | | | | | | | | | | | | | The definition for the AT26DF321 has been commented out since it was first added in 2008. The chip now appears to be obsolete, being marked "obsolete" and unstocked at Digikey. It is also only referred to in historical documents on the manufacturer's website (microchip.com). To avoid further bitrot of this dead code, drop it. Signed-off-by: Alan Green <avg@google.com> Change-Id: Ib30b3a16f25de5def508d90ec9375563b1d4d384 Reviewed-on: https://review.coreboot.org/c/flashrom/+/33836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips.c: format block_erasers membersAlan Green2019-07-031-54/+102
| | | | | | | | | | | | | | | | | To allow automated tools to manipulate flashchips.c, ensure all .block_erasers definitions have consistent formatting: - start with the opening brace on a new line. - ensure end brace indented exactly two tabs. SFDP-capable chip is the one exception to this rule as it has an empty block instead. Signed-off-by: Alan Green <avg@google.com> Change-Id: Ib168bdbbef4cf097109805de15c97ecc1f7915b3 Reviewed-on: https://review.coreboot.org/c/flashrom/+/33831 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: Make end of line comments consistentAlan Green2019-07-021-21/+21
| | | | | | | | | | | | | To allow automated tools to manipulate flashchips.c, make end of line comment formatting more consistent. Specifically, this change moves the comma from end of line to immediately after the field value, before the commment. Signed-off-by: Alan Green <avg@google.com> Change-Id: Ic4f97454766eff640b26a6c6eca29dc56c34c444 Reviewed-on: https://review.coreboot.org/c/flashrom/+/33830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips.c: ATMEL->Atmel for consistencyAlan Green2019-07-021-1/+1
| | | | | | | | | | | | Replace the single instance where a vendor name was spelled inconsistently. Signed-off-by: Alan Green <avg@google.com> Change-Id: I6478bc29f640f789f3b35e7b4816133f4a0d292e Reviewed-on: https://review.coreboot.org/c/flashrom/+/33829 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: Make whitespace consistentAlan Green2019-07-021-98/+101
| | | | | | | | | | | | | | | For consistency, and to make the file amenable to manipulation by tools, use only tabs when indenting. Some previous changes had introduced spaces for indenting. Also ensure that every table entry is separated by a single blank line. Signed-off-by: Alan Green <avg@google.com> Change-Id: Ib2193798cc52641d6c443f8851903c749b31cb74 Reviewed-on: https://review.coreboot.org/c/flashrom/+/33828 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add support for MX25U25635FDavid Tomaschik2019-06-281-0/+49
| | | | | | | | | | | This is a 256Kb part with support for JEDEC 4 byte addressing modes. Tested successfully for probe/read. Change-Id: I5bdcd32acd1942edf65e50bce0f81c836095ee8c Signed-off-by: David Tomaschik <davidtomaschik@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Add Sanyo LE25FU206/A and LE25FU106BAngel Pons2018-11-011-0/+100
| | | | | | | | | | | As per user `The_Raven Raven` on the mailing list. Since the added values had some inconsistencies, the chips are marked as untested. Change-Id: I6c26aafdca232110986334e85297d73d513600dc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Add IS25LP256 and IS25WP256David Hendricks2018-10-301-0/+100
| | | | | | | | | | | Tested IS25LP256 using Raspberry Pi and Dediprog SF600 programmers. Tested IS25WP256 using Dediprog SF600. Change-Id: Idf7a224abcde5f7935d9ef88309f78207de60a7a Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/29306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Add W25Q256JV supportDavid Hendricks2018-10-291-0/+47
| | | | | | | | | | | | | | Similar to W25Q256FV, but it supports the native 4BA page program instruction (12h). Note that the variant with QE enabled by default shares the device ID of the W25Q256FV. Tested using a Raspberry Pi. Change-Id: I76d7362777d364594d2a733d7e478741b0bef7c4 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/29305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark MX25L25635F as testedKasper Revsbech2018-10-231-1/+1
| | | | | | | | | | As reported by Kasper Revsbech on 2018-10-19. Change-Id: Icf05288c4e7e34af2e3f4b951457df695078847d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/29202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Add Macronix MX25U8032EAngel Pons2018-10-071-0/+40
| | | | | | | | | | As per `The_Raven Raven` on the mailing list. Change-Id: I422c3d51e5011e081ff6bccff294817c8c1765d0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Add W25Q128.V..WPatrick Rudolph2018-10-051-0/+37
| | | | | | | | | | | Port the code from chromeos flashrom. Tested using W25Q128JVSIM in SPI mode. Change-Id: I38397a0c831407afa21cddca8485664576fce92c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/28910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark S25FL208K as testedNico Huber2018-10-041-1/+1
| | | | | | | | | | As report by Frédéric Germain on 2017-12-17. Change-Id: I0a7fc10e75f4a675de41e9765525defe2d2640e4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashchips: Add ISSI IS25WP064 and IS25WP032Nico Huber2018-10-041-1/+86
| | | | | | | | | | | | The IS25WP064 was tested successfully by Simon Buhrow as reported on 2018-9-4. While we are at it, also add the 32Mbit version which shares the datasheet (as does the already supported 128Mbit version). Change-Id: Ie0887b4ae6e6465118a5dc2e20b784f783d161b8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashchips: Add ATMEL AT25SL128AHal Martin2018-10-031-0/+39
| | | | | | | | | Change-Id: I60c433ffe9e34663c2cfc608b8b76943cd92a8ba Signed-off-by: Hal Martin <hal.martin@gmail.com> Reviewed-on: https://review.coreboot.org/26576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Enable native 4BA instructions for Spansion 25FL256SNico Huber2018-10-031-1/+4
| | | | | | | | | Change-Id: I0ffc816ca714ecce5b89b1eaadb5e73ccb38d9ab Signed-off-by: Nico Huber <nico.h@gmx.de> Tested-by: Michael Fuckner <michael@fuckner.net> Reviewed-on: https://review.coreboot.org/25134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* Enable 4BA mode for Spansion 25FL256SNico Huber2018-10-031-1/+1
| | | | | | | | | | | 4BA mode is entered by setting bit 7 for the extended address register. Change-Id: I807bf55d65763a9f48a6a3377f14f4e5288a7a4c Signed-off-by: Nico Huber <nico.h@gmx.de> Tested-by: Michael Fuckner <michael@fuckner.net> Reviewed-on: https://review.coreboot.org/25133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* flashchips: Add Spansion 25FL256S......0Nico Huber2018-10-031-0/+42
| | | | | | | | | | | | | | | | The Spansion 25SFL256S supports 4BA through an extended address register, a 4BA mode set by bit 7 of that register, or native 4BA instructions. Enable the former only for now. Unfortunately the S25SF256S uses another instruction to write the exten- ded address register. So we add an override for the instruction byte. Change-Id: I0a95a81dfe86434f049215ebd8477392391b9efc Signed-off-by: Nico Huber <nico.h@gmx.de> Tested-by: Michael Fuckner <michael@fuckner.net> Reviewed-on: https://review.coreboot.org/25132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* flashchips: Mark Spansion S25FL128P......0 as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | Tested with a Spansion FL128PIF. Change-Id: Ic99eabb67d5bce3910e9275d0056a7cfa8cff36f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark Atmel AT45DB081D as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As per `The_Raven Raven` on the mailing list. Change-Id: I225984b9e2589713f25d0f9b49eb1c3abdcff3cd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark Winbond W25Q40BW as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | | | | As per `The_Raven Raven` on the mailing list. The tested chip was `W25Q40.W`, but it was later renamed to `W25Q40BW` when the `W25Q40EW` was added. Change-Id: I624adef2c5b4dd83f0ce93d6069e315fc407db19 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark PMC Pm25LD040 as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As per `The_Raven Raven` on the mailing list. Change-Id: Ied8d07c54f8a222dbe05503f859f82bba27d8336 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark Sanyo LE25FU406C as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As per `The_Raven Raven` on the mailing list. Change-Id: I1dba38d03c826a53bff3ddad0aa536032c5532a1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark PMC Pm25LD020 as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As per `The_Raven Raven` on the mailing list. Change-Id: I16d5a207599b434fe52b42709e42f1f32a8e6698 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark GigaDevice GD25Q128C as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As per Tomasz Walach on the mailing list. Change-Id: Ib0d7485c7221f92ec13995c58065a48e08f57cd8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark AMIC A25L40PU as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As per Stefan Szwarnowski on the mailing list. Change-Id: I574094bdb83611a3cda2fcc455bcf9aed3774011 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark Winbond W25Q256.V as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As per Richard Hughes via the mailing list. Change-Id: Ic562a65d1a7d394f9d2c3980833d10a87bd9358a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark Macronix MX66L51235 as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As per Nick (cel366) on 2018-05-16 via mailing list. Change-Id: I44363e6755167adbc120444a481b09bb4e1063c5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark Atmel AT25DF161 as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As per Konstantin on 2018-06-08 via mailing list. Change-Id: I75fb4b17cf330451489811ae9303cbb33ebcb183 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark Macronix MX25U12835F as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | | | | As reported by David Martinka on the mailing list. Erase has not been tested, but since writes are reported as working, it is very likely erase works as well. Change-Id: I172453fe902ccface2a3a85817d775d45dd7cf80 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28812 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark Eon EN25S40 as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As reported by `The_Raven Raven` on the mailing list. Change-Id: I00f9c6fcf13c486765d0ac4fe06a8b0989b03f91 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark GigaDevice GD25B128B/GD25Q128B as testedAngel Pons2018-10-031-2/+2
| | | | | | | | | | | | Alexander reported this chip as tested using a GD25B128CPIG (same device ID, apparently) on 2018-08-30 via the mailing list. The chip name is updated as well. Change-Id: I134d3816c0f02e20764ab132a01bcba9f4e93f0d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Add ISSI IS25LP064Angel Pons2018-10-031-0/+41
| | | | | | | | | | | Grabbed from mailing list, created by Simon Buhrow. Since no logs were attached, the chip is marked as untested. Change-Id: Idc26162fc5a5a429acef546b30b12d8b1f195e0a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark Micron MT25QL512 as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As reported by `Yuta Teshima` on the mailing list. Change-Id: I7325d42b43b71ab5fc2c7618e0577e4a7b31f01a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Fix typosElyes HAOUAS2018-08-191-3/+3
| | | | | | | | Change-Id: I20745d5f30f9577622e27abf2f45220f026f65ac Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark GigaDevice GD25Q512 as testedNico Huber2018-08-191-1/+1
| | | | | | | | | | As reported by `nvflash` on IRC. Change-Id: Id3928e3790ddac34645959535e646d552ce5328e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at>
* Add support for MX25R6435FNathan Rennie-Waldock2018-08-171-0/+39
| | | | | | | | | Change-Id: I664ffce6f9aa7544e17b516a1b4179d561208b2f Signed-off-by: Nathan Rennie-Waldock <nathan.renniewaldock@gmail.com> Reviewed-on: https://review.coreboot.org/28004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Add Macronix MX25U51245GDaniel Thompson2018-08-171-0/+49
| | | | | | | | | | | | | | | | Copy 'n paste support for Macronix MX25U51245G. I don't pretend to know a whole lot about SPI FLASH so its mostly copied from other MX25U devices and double checked a few bits and pieces against the datasheet. I have tested basic probe, read, erase and write using layout files. I tested both with 4MB@0x0000000 and 64K0@0x3f00000 (the later means I have tested 4-byte addressing). Change-Id: I2117fc205006088967f3d97644375d10db1791f1 Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Reviewed-on: https://review.coreboot.org/26949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Add support for AT25DF021ASteffen Mauch2018-06-061-0/+39
| | | | | | | | | | | This is the low-voltage version of the AT25DF021. Tested with FT2232H Mini Module Change-Id: If4990e6856c8b77567ef4218459cf754b9c6bc57 Signed-off-by: Steffen Mauch <steffen.mauch@gmail.com> Reviewed-on: https://review.coreboot.org/26856 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add support for the AT25SF081Evan Jensen2018-06-041-0/+38
| | | | | | | | Change-Id: I1a3d900462ad9e7a3b34575d7c98acc7c2df0445 Signed-off-by: Evan Jensen <evan.p.jensen@gmail.com> Reviewed-on: https://review.coreboot.org/26779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* flashchips: Add Winbond 25Q40EW and rename 25Q40.WNico Huber2018-05-061-2/+42
| | | | | | | | | | | Same story as for 25Q80BW/EW, 25Q40EW has a new ID and the only known chip with the old ID is the BW variant. Change-Id: Ib610b0d6f3a5561b2ac3505ef15bdee8b0edae25 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/25462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* flashchips: Add SST26VF016B(A), SST26VF032B(A), SST26VF064B(A)Wei Hu2018-05-061-0/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch seems to have originally been from https://patchwork.coreboot.org/patch/4126/ . The most recent version seems to be in OpenEmbedded (commit 503a572) which added support for 16Mbit and 32Mbit variants. The OpenEmbedded patch also makes changes to linux_spi.c to add some debug prints which are omitted in this version. From the original commit message: Differences between SST26 and SST25: 1. The WREN instruction must be executed prior to WRSR [Section 5.31]. There is no EWSR. 2. Block protection bits are no longer in the status register. There is a dedicated 144-bit register [Table 5-6]. The device is write-protected by default. A Global Block-Protection Unlock command unlocks the entire memory [Section 4.1]. Change-Id: Ib019bed8ce955049703eb3376c32a83ef607c219 Signed-off-by: Wei Hu <wei@aristanetworks.com> Signed-off-by: David Hendricks <david.hendricks@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Reviewed-on: https://review.coreboot.org/25962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Remove address from GPLv2 headersElyes HAOUAS2018-04-241-4/+0
| | | | | | | | Change-Id: I7bfc339673cbf5ee2d2ff7564c4db04ca088d0a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Fix whitespace errorsElyes HAOUAS2018-04-241-2/+2
| | | | | | | | Change-Id: Ic2d3bb9d8581a0471a8568a130f893b34dddf113 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-01 23:44:10 +0000