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* flashchips: Add support for XMC XM25QH80BHEADmasterSungbo Eo2023-09-221-0/+38
| | | | | | | | | | | | XM25QH80B has the same ID as M45PE80, but has more features. Tested with CH341A. Change-Id: Ib51225426d8d1a381d45af3574e5ba2bf02837aa Signed-off-by: Sungbo Eo <mans0n@gorani.run> Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/63516 Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Add support for MXIC MX25U25643Gxianzheng2023-09-171-1/+1
| | | | | | | | | | | | | | | It is similar to the MX25U25635F and shares its RDID. Tested by ch341a programmer : read, write and erase. Datasheet is available at the following URL: https://www.mxic.com.tw/en-us/products/NOR-Flash/Serial-NOR-Flash/Pages/spec.aspx?p=MX25U25643G&m=Serial%20NOR%20Flash&n=PM2832 Change-Id: Ie04a5e2325aab94bffb276675be3fa4a88c6e134 Signed-off-by: xianzheng <xianzheng@mxic.com.cn> Reviewed-on: https://review.coreboot.org/c/flashrom/+/76853 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: add definition of the XT25F02E SPI NOR flashNeil Armstrong2023-09-161-0/+35
| | | | | | | | | | | | | | | | | This adds definition of the XT25F02E 2MBit SPI NOR Flash from XTX Technology Limited. Tested (Probe, Erase, Write, Read) with a VL805 USB3.0 bridge. Datasheet: https://datasheet.lcsc.com/lcsc/2006091008_XTX-XT25F02EDTIGT_C596313.pdf Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Change-Id: I295633c448c05520e4a6aa09c08bd7c9f2346d54 Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/50263 Reviewed-by: Peter Marheine <pmarheine@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Add WP features for Winbond W25X20Vasily Galkin2023-09-031-1/+8
| | | | | | | | | | | | | | WP-related registers list from official datasheet https://www.winbond.com/resource-files/w25x20cl_revf%2020150806.pdf Commandline options tested with ft2232_spi-based "Tigard" programmer: wp-disable wp-enable wp-list wp-status wp-range=0,0 wp-range=0,0x00040000 Signed-off-by: Vasily Galkin <galkin-vv@ya.ru> Change-Id: I82c0cc52ca2a78d27f513234cc12d3e09d8905a5 Reviewed-on: https://review.coreboot.org/c/flashrom/+/77530 Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: Add support for IS25WQ040Vasily Galkin2023-08-301-0/+40
| | | | | | | | | | | | | | | Based on https://github.com/flashrom/flashrom/pull/204 squashed with fixes of IS25WQ040 size: it is 4Mbits, not 4MBytes, see https://www.issi.com/WW/pdf/25WQ020-040.pdf Tested read, write and erase with ft2232_spi-based "Tigard" programmer. Change-Id: I072c6b94d7931637d1c2721c3316205f2d57320e Signed-off-by: Roman Stingler <roman.stingler@gmail.com> Signed-off-by: Vasily Galkin <galkin-vv@ya.ru> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58179 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: add Macronix MX25L3255EJoseph C. Lehner2023-08-231-0/+40
| | | | | | | | | | | | | | Tested using the linux_spi programmer on a Raspberry Pi. Datasheet: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L3255E.pdf Signed-off-by: Joseph C. Lehner <joseph.c.lehner@gmail.com> Change-Id: I65968771e22e6b823d2d6192c33f5b0cba25d5b9 Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/57410 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Add ISSI IS25LQ016Angel Pons2023-08-151-0/+40
| | | | | | | | | | | | Datasheet: http://www.issi.com/WW/pdf/25LQ016.pdf Tested all four PREW functions with a FT2232H. Change-Id: I02f19767b8a60fb2d37adab34894b6edb6ac4494 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
* flashchips: Add XTX XT25F64BWereCatf2023-07-171-0/+40
| | | | | | | | | | | | | Datasheet: http://file2.dzsc.com/product/19/06/22/216185_132959081.pdf Tested probe, read, erase and write with CH341a. Signed-off-by: Nita Vesa <werecatf@outlook.com> Change-Id: I369db9ccfd5319d28424d10f77aab49ec73a8836 Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* flashchips: add support for MX77L25650F chipArtur Kowalski2023-07-121-0/+40
| | | | | | | | | | | | | Add initial support for Macronix MX77L25650F. Can read, write and erase the chip. Change-Id: Iaea5485f8b59b8538dc47beada2c308376ea027c Signed-off-by: Artur Kowalski <artur.kowalski@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Signed-off-by: ServError <admin@serverror.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips.c: Adding support for ISSI IS25WP020/40/80Ao Zhong2023-07-121-0/+126
| | | | | | | | | | | | | | | | | | This patch added support for IS25WP020, IS25WP040, and IS25WP080 SPI flash chips. The datasheet for these chips can be found at: https://www.issi.com/WW/pdf/25WP016_080_040_020.pdf Tested read, write, and erase functions on IS25WP080. Test log: Write: https://paste.flashrom.org/view.php?id=3698 Write test 2: https://paste.flashrom.org/view.php?id=3699 Erase: https://paste.flashrom.org/view.php?id=3700 Change-Id: I8a786de5cf9ffefb2d57f89bbab71e289b5c2b28 Signed-off-by: Ao Zhong <hacc1225@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/75830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips: add support for MX25V16066/KH25V16066Joseph Goh2023-06-301-0/+38
| | | | | | | | | Change-Id: Ic5f0548f023fcd09a970148586497e00414ad1ae Signed-off-by: Joseph Goh <josephgoh7@gmail.com> Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips: Add support for XMC XM25QH128AStijn Segers2023-06-211-0/+48
| | | | | | | | | | | | | | | | Tested: read, write and erase. Chip (and datasheet) have recenty been removed from XMC's website but can still be retrieved through web archive: https://web.archive.org/web/20221122191724/https://www.semiee.com/file/XMC/XMC-XM25QH128A.pdf Signed-off-by: Stijn Segers <foss@volatilesystems.org> Change-Id: Iced40403c6694a55fd648ea2785cdcba21712234 Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69309 Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips: add support for ISSI IS25LP016Mario Kicherer2023-06-161-0/+41
| | | | | | | | | | | | | | I took the original patch from Ondrej Hennel [1] and applied the requested changes. Reading, erasing and writing works. [1] https://patchwork.ozlabs.org/project/flashrom/list/?series=261647 Change-Id: Iffd7c4284d4d96b30a94f5dee882b5403fdfc183 Signed-off-by: Mario Kicherer <dev@kicherer.org> Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
* flashchips: Add AT25DF011Hanno Heinrichs2023-06-161-0/+39
| | | | | | | | | | | | | Tested read/write/erase/probe operations with a ch341a_spi programmer. Datasheet is available at https://www.mouser.de/datasheet/2/590/DS-AT25DF011_032-1098683.pdf Signed-off-by: Hanno Heinrichs <hanno.heinrichs@rwth-aachen.de> Change-Id: I5a2141f1380e864c843d6a3008fdb02dc1b75131 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/51048 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Mark S25FL128L as tested for probe, read, write, eraseAnastasia Klimchuk2023-06-111-1/+1
| | | | | | | | | | | As reported on the mailing list: https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/3CC54GMEBXYVOXBJ7J5NZ5R4SQ42ZOXC/ Change-Id: I0700d3e4f684db096fea63eb9bc5add44e246758 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/75604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* flashchips: Add support for IS25WP016Alex Mikhalev2023-06-081-0/+42
| | | | | | | | | | | | | | Tested reading, writing and erasing using `linux_spi` programmer on Raspberry Pi CM4. Datasheet: https://web.archive.org/web/20221129211027/https://www.issi.com/WW/pdf/25LP-WP016D.pdf Change-Id: I2b8caea229ffda72f1b04183c31715faccb64ad5 Signed-off-by: Alex Mikhalev <alex@corvus-robotics.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70140 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Add support for Boya BY25D80APiotr Halama2023-06-081-0/+38
| | | | | | | | | | Read tested on Raspberry Pico with pico-serprog Change-Id: I586f3455d925132bbda3fccdad00f0b1e22c2ea7 Signed-off-by: Piotr Halama <skrzynka@halamix2.pl> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* flashchips.c: Add write protect support for W25Q16.VKhoa Hoang2023-06-051-2/+12
| | | | | | | | | | | | | | | | Enable WRSR2 feature flag and define reg_bits and decode_range for W25Q16.V to enable write protect support. Based on W25Q16DV, Revision: 1, Release: Nov 18 2014 datasheet TEST=flashrom --wp-{enable,disable,range,list,status} Change-Id: I6c0b35f82b47a1169bccfd08222e9e3b3be30d75 Signed-off-by: Khoa Hoang <admin@khoahoang.com> Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
* tree/: Case write_granularity enum valuesEdward O'Callaghan2023-04-061-3/+3
| | | | | | | | Change-Id: Ic8c655225abe477c1b618dc685b743e691c16ebd Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/74165 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Add Macronix MX25V1635F supportPoroCYon2023-03-261-0/+35
| | | | | | | | | | | | | | | See https://www.mxic.com.tw/Lists/Datasheet/Attachments/8662/MX25V1635F,%202.5V,%2016Mb,%20v1.4.pdf . I've tested this patch with the MX25V1635F I have here, using serprog and ftdi by (re)writing a few images to the flash and seeing if changes were stored correctly. This also included erasing and rewriting the memory with completely different data, so erase is tested, too. Change-Id: I58ddaaa96ef410d50dde3aaa20376c5bbf0f370b Signed-off-by: PoroCYon <p@pcy.be> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips: Add Macronix MX25V8035F supportPoroCYon2023-03-261-0/+35
| | | | | | | | | | | | | | | See https://www.macronix.com/Lists/Datasheet/Attachments/8405/MX25V8035F,%202.5V,%208Mb,%20v1.0.pdf . I've only tested this patch with the MX25V1635F I have here, though other chips in the series exist as well. Tested using serprog and ftdi by writing a few images to the flash and seeing if changes were stored correctly. Change-Id: Ic5be2da4cfa2a2ff044a519bb6f367f21c15e4b8 Signed-off-by: PoroCYon <p@pcy.be> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips: Add Macronix MX25V4035F supportPoroCYon2023-03-261-0/+36
| | | | | | | | | | | | | | | See https://www.macronix.com/Lists/Datasheet/Attachments/8670/MX25V4035F,%202.5V,%204Mb,%20v1.2.pdf . I've only tested this patch with the MX25V1635F I have here, though other chips in the series exist as well. Tested using serprog and ftdi by writing a few images to the flash and seeing if changes were stored correctly. Change-Id: I8b26926c354b840ca7b14b4c5cb000e3c02f5137 Signed-off-by: PoroCYon <p@pcy.be> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips: Mark AM29LV040B as write-testedAnastasia Klimchuk2023-03-061-1/+1
| | | | | | | | | | | | | Reported by Alex Perez on the mailing list, write operation done successfully with satasii programmer. https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/67OX4CSBGWAGMNGEOATBJGFJCKFD64SU/ Change-Id: I8a42f8214b09c455a10a1f1e9e69feaeca2c62a1 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashchips: Mark XMC XM25QH64C as TEST_OK_PREWThomas Heijligen2023-03-061-1/+1
| | | | | | | | | | | | | As reported on the mailing list[0] this flashchip was successfully probed, read, erased and written with a ch341a programmer. [0] https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/message/SMIHEXHZBSCGE2Y2EG75XQHWSKEQ3PP6 Change-Id: Ifca84d9a44bb20091293356f5b1643de41220b64 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips: Mark XMC XM25QH256C as TEST_OK_PRThomas Heijligen2023-03-061-1/+1
| | | | | | | | | | | | | As reported on the mailing list[0] this flashchip was successfully probed and read with a ch341a programmer. [0] https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/message/BFBKAJKURZHYQ6OTV3UAA7V5O2ZSJWGN Change-Id: I68d0315f7b29f27ac84374ea7cc69dca207bbacb Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips.c: Add reg_bits for W25Q256JW_DTRKapil Porwal2023-02-211-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | Add reg_bits for W25Q256JW_DTR as per the datasheet. BUG=b:263410331 TEST=Verified on google/rex. w/o this patch: Failed to get WP status: WP operations are not implemented for this chip w/ this patch: flashrom -p internal --wp-range 0x0,0x2000000 flashrom -p internal --wp-enable flashrom -p internal --wp-status flashrom -p internal -E <---- failed to erase the flash as WP (which is expected) Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I8ac23f706d4293a7d7d11ad6b2f62526fb075367 Reviewed-on: https://review.coreboot.org/c/flashrom/+/70549 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Remove FEATURE_4BA_WREN for MT25QL128 and mark as testedRick Altherr2023-01-151-2/+2
| | | | | | | | | | | | | | | | | Using both a Dediprog SF100 and a Bus Pirate, read and erase works correctly on a MT25QL128 but writes were failing to take effect. Currently, the entry in flashchips.c indicates that this device supports 4-byte addressing. Micron's datasheet indicates that it does not. After removing FEATURE_4BA_WREN from feature_bits, both SF100 and Bus Pirate were able to successfully read, erase, and write a MT25QL128 so also marking as tested. Change-Id: I6341456c722840a413bd2c51fe9a78bbda5cdbab Signed-off-by: Rick Altherr <kc8apf@kc8apf.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips.c: Mark W25Q128.V WP as testedEdward O'Callaghan2022-12-191-1/+1
| | | | | | | | | | | | BUG=b:258755442 TEST=`-p internal --wp-status`. Change-Id: Ifbd5ee76f2087764ab8841ca96de6990cb31260d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70866 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Add WP settings for Flash Chip `W25Q512NW`Subrata Banik2022-12-161-2/+13
| | | | | | | | | | | | | | | | | This patch adds WP register bits and decode range for Flash Chip `W25Q512NW`. TEST=Able to flash AP FW, wp-enable/disable on Google/rex device which has flash chip `W25Q512NW`. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic5148f71404466dcf7772e3eb6e1800eb8666696 Reviewed-on: https://review.coreboot.org/c/flashrom/+/67827 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
* flashchips.c: Indent definition of W25Q512NW-IM properlyFelix Singer2022-12-161-40/+40
| | | | | | | | Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: Icfd2a49383da0f8f0a4e3295aba81ce1d200652c Reviewed-on: https://review.coreboot.org/c/flashrom/+/68151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* flashchips.c: remove WREN from GD25Q256D enter 4BA sequenceNikolai Artemiev2022-12-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | As noted in a comment on `commit 86fc9cf7ab221bc54ef6f10252e296fc2d7a22d2`, the GD25Q256D datasheet indicates that the chip does not require a WREN command to enter 4BA mode. Testing has confirmed that a WREN command is not required, so change the flashchip feature flags from FEATURE_4BA_WREN to FEATURE_4BA. Ticket: https://ticket.coreboot.org/issues/356 BUG=none BRANCH=none TEST=read/write/erase/verify GD25Q256D flash with FT2232H programmer TEST=called spi_enter_exit_4ba(true), dumped registers, checked ADS=1. Change-Id: I96e48933f33c52c0d10a0d4cb7f7e07c1fceab99 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips.c: Add 4BA write to XM25Qx256CLiam Flaherty2022-12-011-2/+3
| | | | | | | | | | | | | | | | | | | Flash chips XM25QH256C and XM25QU256C support the 4-byte program command (0x12) according to their datasheets, but the feature flag is not enabled in flashchips.c, so enable it to allow this feature to be used. TICKET: https://ticket.coreboot.org/issues/371 BUG=b:259493706 TEST=build Change-Id: I96c80762fcda2af6028c7a53d8c545b0c6565cbd Signed-off-by: Liam Flaherty <liamflaherty@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69713 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tree/: Convert flashchips db to use indirection for printlockNikolai Artemiev2022-11-231-408/+408
| | | | | | | | | | | | | | This paves the way to allow for the conversion of flashchip printlock func ptr to enumerate values. This change should be a NOP. TEST=`diff -u <(objdump -D flashchips.o_bk) <(objdump -D flashchips.o)`. Change-Id: Icff868d9454e9b0a059a736457bb562430436033 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* tree/: Convert flashchips db to use indirection for unlockEdward O'Callaghan2022-11-231-421/+421
| | | | | | | | | | | | | This paves the way to allow for the conversion of flashchip unlock func ptr to enumerate values. This change should be a NOP. TEST=`diff -u <(objdump -D flashchips.o_bk) <(objdump -D flashchips.o)`. Change-Id: I3ed51142cd22becc8286959f5504565158fa2de0 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* flashchips.c: enable WP for 7 entries of MX chipsSergii Dmytruk2022-11-191-4/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These weren't split: * MX25L3206E/MX25L3208E Tested: https://github.com/Dasharo/flashrom/pull/8 * MX25L6405 * MX25L6405D * MX25L6406E/MX25L6408E Tested: https://github.com/Dasharo/flashrom/pull/8 MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E/MX25L6473F was split into: * MX25L6436E/MX25L6445E/MX25L6465E - security register - WPS - tested: https://github.com/Dasharo/flashrom/pull/8 * MX25L6473E - security register - OTP TB bit in CONFIG/STATUS2 (0x15 opcode) - WPS * MX25L6473F - NO security register - OTP TB bit in CONFIG/STATUS2 (0x15 opcode) - NO WPS Change-Id: Ib3db9d39ffacd3e9e44de92c6cfb6c3ecc8615bd Tested-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips.c: enable WP for MT25QL512, N25Q0{32,64}..{1,3}ESergii Dmytruk2022-11-191-0/+51
| | | | | | | | Change-Id: Ib0f3cb9516cea7bb678842a358a82099221e1ed9 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66215 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: enable WP for W25Q32.V, W25Q32.W and W25Q32JW...MSergii Dmytruk2022-11-191-6/+248
| | | | | | | | | | | | Split chips: * W25Q32.V -> W25Q32BV/W25Q32CV/W25Q32DV, W25Q32FV and W25Q32JV * W25Q32.W -> W25Q32BW/W25Q32CW/W25Q32DW, W25Q32FW and W25Q32JW...Q Change-Id: Id259c27dfa6c681bbadc73b3bd7559ad6a5865f4 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips.c: enable WP for EN25QH32 and EN25QH64Sergii Dmytruk2022-11-191-0/+96
| | | | | | | | | | | | | | | Split chips: * EN25QH32 -> EN25QH32 and EN25QH32B * EN25QH64 -> EN25QH64 and EN25QH64A Unlike older revisions both newly added EN25QH32B and EN25QH64A support half block (32KiB) erase operation via 0x52 opcode. Change-Id: I759f0119346235ce0bddc78cde9c461495990c25 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tree/: Convert flashchips db to use indirection for erase_blockEdward O'Callaghan2022-11-111-1938/+1938
| | | | | | | | | | | | | | This paves the way to allow for the conversion of flashchip erase_block func ptr to enumerate values. This change should be a NOP. TEST=`diff -u <(objdump -D flashchips.o_bk) <(objdump -D flashchips.o)`. Change-Id: I122295ec9add0fe0efd27273c9725e5d64f6dbe2 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69131 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Add write protect bits to W25Q64JW...MEvan Benn2022-11-101-1/+12
| | | | | | | | | | | | | | | https://www.winbond.com/hq/support/documentation/levelOne.jsp?__locale=en&DocNo=DA00-W25Q64JW BUG=b:245996788 BRANCH=None TEST=None Change-Id: Idf2289b7c90724ececc122d2a05c7cae3af2cf62 Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
* tree/: Convert flashchip read func ptr to enumerateEdward O'Callaghan2022-11-011-587/+587
| | | | | | | | | | | | | | | | This forges the way for flashchips.c to be pure declarative data and lookup functions for dispatch to be pure. This means that the flashchips data could be extracted out to be agnostic data of the flashrom code and algorithms. TEST='R|W|E && --flash-name' on ARM, AMD & Intel DUT's. Change-Id: I612d46fefedf2b69e7e2064aa857fa0756efb4e7 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66788 Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/: Convert flashchip write func ptr to enumerateEdward O'Callaghan2022-11-011-589/+589
| | | | | | | | | | | | | | | | This forges the way for flashchips.c to be pure declarative data and lookup functions for dispatch to be pure. This means that the flashchips data could be extracted out to be agnostic data of the flashrom code and algorithms. TEST='R|W|E && --flash-name' on ARM, AMD & Intel DUT's. Change-Id: I80149de169464b204fb09f1424a86fc645b740fd Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* tree/: Convert flashchip probe func ptr to enumerateEdward O'Callaghan2022-11-011-592/+592
| | | | | | | | | | | | | | | | This forges the way for flashchips.c to be pure declarative data and lookup functions for dispatch to be pure. This means that the flashchips data could be extracted out to be agnostic data of the flashrom code and algorithms. TEST='R|W|E && --flash-name' on ARM, AMD & Intel DUT's. Change-Id: I00aaab9c83f305cd47e78c36d9c2867f2b73c396 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* tree/: Convert flashchip decode range func ptr to enumNikolai Artemiev2022-10-281-22/+22
| | | | | | | | | | | | | | | | | | | | Replace the `decode_range` function pointer in `struct flashchip` to an enum value. The enum value can be used to find the corresponding function pointer by passing it to `lookup_decode_range_func_ptr()`. Removing function pointers like `decode_range` makes it possible to represent chip data in a declarative format that does not have to be stored as C source code. BUG=b:242479049 BRANCH=none TEST=ninja && ninja test Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Change-Id: If6d08d414d3d1ddadc95ca1d407fc87c23ab543d Reviewed-on: https://review.coreboot.org/c/flashrom/+/67195 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: mark WP of 9 entries as testedSergii Dmytruk2022-10-231-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is based on information from: * commit a850fd0aa8054a1125a9231fa3317428f15900f4 - GD25LQ128C/GD25LQ128D/GD25LQ128E - GD25LQ64(B) - GD25Q127C/GD25Q128C - GD25Q256D/GD25Q256E - GD25Q64(B) * commit a8204dd34d90ac9ab2783e1dd486ec781d4c0dba - GD25Q32(B) * commit 7b4c4f36113c4b7ed5c985d4cf51733639e69bf8 - W25Q64BV/W25Q64CV/W25Q64FV * https://github.com/Dasharo/dasharo-issues/issues/67 - W25Q128.V..M * https://github.com/Dasharo/flashrom/pull/8 - W25Q64.W Change-Id: I090188bad568885f78778e7fc7d8dbe20fb2445f Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Tested-by: Nikolai Artemiev <nartemiev@google.com> Tested-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Tested-by: Kamil Pokornicki <kamil.pokornicki@3mdeb.com> Tested-by: Przemyslaw Banasiak <przemyslaw.banasiak@3mdeb.com> Tested-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68180 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: Mark MT25QU256 as testedAngel Pons2022-07-051-1/+1
| | | | | | | | | | | | As reported by Charles Parent on the mailing list. Change-Id: I9d8b0038673185103ba08c9797ff94f2f7639d6c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62664 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: change GD25Q256D to "GD25Q256D/GD25Q256E"Nikolai Artemiev2022-07-051-1/+1
| | | | | | | | | | | | | | | | Extend "D" chip entry to include newer "E" parts. BUG=b:234054642 BRANCH=none TEST=builds Change-Id: I6b398d417da9289cc1d6a191fb20e3f937addb21 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65191 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashchips: Add missing block eraser for S25FL512SNico Huber2022-06-231-0/+3
| | | | | | | | | | | | | Now that we can make use of the extended-address register, we can also advertise the `d8` eraser that can take 3- or 4-byte addresses. Signed-off-by: Nico Huber <nico.h@gmx.de> Ticket: https://ticket.coreboot.org/issues/357 Change-Id: I8708294d42f5da80c0ca07ccdae627f13fd5c645 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64637 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashchips: Enable FEATURE_4BA_EAR_1716 for S25FL512SNico Huber2022-06-231-2/+3
| | | | | | | | | | | | | | | | According to its datasheet, Spansion S25FL512S supports writing/ reading its extended address register via 0x17/0x16 opcodes. With that enabled, we can also enable the EAR7 feature, i.e. toggling 4BA mode via bit 7 of that register. S25FL512S did not advertise EAR support at all, so we set it to TEST_UNTESTED again. Change-Id: Ib214e509a5c294ab60460a2b5d00a713a119ab3f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashchips: Enable FEATURE_4BA_EAR_1716 for ISSI chipsNico Huber2022-06-231-2/+4
| | | | | | | | | | | | | | | | | According to their datasheets, ISSI IS25LP256 and IS25WP256 support both 0xc5/0xc8 and 0x17/0x16 opcodes to write / read their extended address register. Flashrom will use 0xc5 by default if available, so adding the FEATURE_4BA_EAR_1716 flag makes no difference for now (FEATURE_4BA_EAR_C5C8 is included in the already selected FEATURE_4BA set). It's better to have a comprehensive description of the chips, though, in case somebody wants to use them in the future with a master that restricts available opcodes. Change-Id: I03e4ff825c7742e7ff79b51b75293d53a091d4d4 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-06 18:24:47 +0000