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* buspirate_spi: Add support for variable serial speedsShawn Anastasio2018-01-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This patch sets the default baud rate for communication between the host device and the Bus Pirate for hardware versions 3.0 and greater to 2M baud. It also introduces the ability to manually set the baud rate via the added 'serialspeed' programmer parameter. This is done in two parts. Firstly, the requested serial speed is looked up in a table to determine the appropriate clock divisor and the divisor is sent to the bus pirate. Then, the system's baud rate for the selected serial port is set using serial.c's 'serialport_config'. This function's prototype had to be added to programmer.h. In testing, using the 2M baud rate was able to significantly decrease flash times (down from 20+ minutes to less than 2 minutes for an 8MB flash). Change-Id: I3706f17a94fdf056063f2ad4a5f0a219665cdcbf Signed-off-by: Shawn Anastasio <shawnanastasio@yahoo.com> Reviewed-on: https://review.coreboot.org/23057 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi_master: Introduce SPI_MASTER_4BA feature flagNico Huber2018-01-021-0/+13
| | | | | | | | | | | | | | | Add a feature flag SPI_MASTER_4BA to `struct spi_master` that advertises programmer-side support for 4-byte addresses in generic commands (and read/write commands if the master uses the default implementations). Set it for all masters that handle commands address-agnostic. Don't prefer native 4BA instructions if the master doesn't support them. Change-Id: Ife66e3fc49b9716f9c99cad957095b528135ec2c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* spi: Move ICH BBAR quirk out of the wayNico Huber2017-12-281-1/+0
| | | | | | | | | | | | | | | | | | | | | Get rid of the layering violations around ICH's BBAR. Move all the weird address handling into (surprise, surprise) `ichspi.c`. Might fix writes for the `BBAR != 0` case by accident. Background: Some ICHs have a BBAR (BIOS Base Address Configuration Register) that, if set, limits the valid address range to [BBAR, 2^24). Current code lifted addresses for REMS, RES and READ operations by BBAR, now we do it for all addresses in ichspi. Special care has to be taken if the BBAR is not aligned by the flash chip's size. In this case, the lower part of the chip (from BBAR aligned down, up to BBAR) is inacces- sible (this seems to be the original intend behind BBAR) and has to be left out in the address offset calculation. Change-Id: Icbac513c5339e8aff624870252133284ef85ab73 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22396 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* chipset_enable: Add support for C620-series Lewisburg PCHDavid Hendricks2017-09-011-0/+1
| | | | | | | | | | | | | | | | This adds PCI IDs for C620-series PCHs and adds CHIPSET_C620_SERIES_LEWISBURG as a new entry in the ich_chipset enum. Lewisburg is very similar to Sunrise Point for Flashrom's purposes, however one important difference is the way the "number of masters" is interpreted from the flash descriptor (0-based vs. 1-based). There are also new flash regions defined. Change-Id: I96c89bc28bdfcd953229c17679f2c28f8b874d0b Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/20922 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* rpci: Use pci_dev struct pointer to avoid API breaksYouness Alaoui2017-08-101-0/+5
| | | | | | | | | | | | | | | | | | | | | | The pci_dev structure is never meant to be used as is, but always as a pointer. By using the struct itself in undo_pci_write_data, we are risking data corruption, or buffer overflows if the structure size changes. This is especially apparent on my system where flashrom segfaults because I compile it with pciutils 3.3.0 and I run it on a system with pciutils 3.5.2. The struture size is different and causes a struct with the wrong size to be sent to the library, with invalid internal field values. This has been discovered and discussed in Change ID 18925 [1] [1] https://review.coreboot.org/#/c/18925/ Change-Id: Icde2e587992ba964d4ff92c33aa659850ba06298 Signed-off-by: Youness Alaoui <kakaroto@kakaroto.homelinux.net> Reviewed-on: https://review.coreboot.org/20784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* chipset_enable: Add support for Intel Skylake / KabylakeNico Huber2017-07-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All publicly known Skylake / Kabylake / Sunrise Point PCH variants share the same register interface [1..6]. Although all SPI configu- ration is now done through the SPI PCI device 1f.5, we can't probe for it directly since its PCI vendor and device IDs are usually hid- den. To work around the hidden IDs, we use another PCI accessor that doesn't rely on the OS seeing the PCI device. This handles SPI flashes only. While booting from LPC is still sup- ported, it seems nobody uses it any more. Some additional PCI IDs were gathered from driveridentifier.com. TEST=Compiled with B150 set to NT (instead of BAD) and checked for sane register readings. [1] 6th Generation Intel® Core(TM) Processor Families I/O Platform Datasheet - Volume 1 of 2 Revision 002EN Document Number 332995 [2] 6th Generation Intel® Processor I/O Datasheet for U/Y Platforms Volume 2 of 2 Revision 001EN Document Number 332996 [3] 7th Generation Intel® Processor Families I/O Platform Datasheet - Volume 1 of 2 Revision 002 Document Number 334658 [4] 7th Generation Intel® Processor Families I/O for U/Y Platforms Datasheet - Volume 2 of 2 Revision 002 Document Number 334659 [5] Intel® 100 Series and Intel® C230 Series Chipset Family Platform Controller Hub (PCH) Datasheet - Volume 1 of 2 Revision 004EN Document Number 332690 [6] Intel® 100 Series Chipset Family Platform Controller Hub (PCH) Datasheet - Volume 2 of 2 Revision 001EN Document Number 332691 Change-Id: I000819aff25fbe9764f33df85f040093b82cd948 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18925 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
* ichspi: Drop `dev` parameter from init functionsNico Huber2017-06-201-2/+2
| | | | | | | | | | | | It's never used and has no clear contract (e.g. will the pointer stay valid beyond the call?). Change-Id: I0d4e7cc731364e86eff214b9022b842a577f9ef4 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Handle Intel Wildcat Point *LP* like Lynx Point LPNico Huber2017-06-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | The subtle difference was ignored when adding these chipsets. The integrated Wildcat Point LP PCH is documented in [1]. I'm not sure how to account for "Broadwell H" which seems not publicly documented. Maybe it's an unreleased HM9*, in which case the non-LP path should be correct. [1] Mobile 5th Generation Intel® Core(TM) Processor Family I/O, Intel® Core(TM) M Processor Family I/O, Mobile Intel® Pentium® Processor Family I/O, and Mobile Intel® Celeron® Processor Family I/O Datasheet Revision 004 Document Number: 330837 Change-Id: I6b7ca3c0bde111b04ed7c745ed76d28d3d05f01c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18883 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* hwaccess: Constify `addr` argument of MMIO read functionsNico Huber2017-04-251-7/+7
| | | | | | | | | | Change-Id: I1419241a8332b74103b3921df2c615bdf91346a7 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18881 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* Make image parameter of cb_check_image constNico Huber2017-01-131-1/+1
| | | | | | | | | Change-Id: I811b3d6f1710154e055b03d5f27b1a8d9b3c0a43 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/17943 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* dediprog: use ordinary USB devs arrayStefan Tauner2016-02-221-0/+1
| | | | | | | | | | Even though there is currently only one USB device ID in the wild using our standard way to define the devices creates nicer output for -L and -z. Corresponding to flashrom svn r1942. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* pickit2_spi: use ordinary USB devs arrayStefan Tauner2016-02-221-0/+1
| | | | | | | | | | Even though there is currently only one USB device ID in the wild using our standard way to define the devices creates nicer output for -L and -z. Corresponding to flashrom svn r1941. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add support for WCH CH341A as an SPI programmerUrja Rannikko2016-01-311-0/+13
| | | | | | | | Corresponding to flashrom svn r1921. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Urja Rannikko <urjaman@gmail.com>
* Add a bunch of new/tested stuff and various small changes 24Stefan Tauner2016-01-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested mainboards: OK: - ASRock G31M-GS Reported by Александр Трубицын - ASRock G41M-VS3 Reported by Александр Трубицын - ASRock N68C-S UCC Reported by Alexey Belyaev - ASRock AMCP7AION-HT (ION 330HT(-BD)) Reported by Stefan Tauner - ASUS P5K SE Reported by Александр Трубицын - ASUS P5KPL-VM Reported by Marin Vlah - ASUS RAMPAGE III GENE Reported by stevessss on IRC - GIGABYTE GA-945GM-S2 Reported by Александр Трубицын - GIGABYTE GA-945GCM-S2 (rev. 3.0) Reported by Александр Трубицын - GIGABYTE GA-965P-S3 Reported by Александр Трубицын - GIGABYTE GA-EG43M-S2H Reported by Александр Трубицын - GIGABYTE GA-EP31-DS3L (rev. 1.0) Reported by Александр Трубицын - GIGABYTE GA-G33M-S2 Reported by Александр Трубицын - GIGABYTE GA-G33M-S2L Reported by Александр Трубицын - GIGABYTE GA-H55M-S2 Reported by Александр Трубицын - GIGABYTE GA-J1900N-D3V Reported by Marcos Truchado and Guillermo von Hünefeld - GIGABYTE GA-K8NS Reported by nicolae788 - GIGABYTE GA-M56S-S3 Reported by Estevo Paz Freire - GIGABYTE GA-P31-DS3L Reported by Александр Трубицын - GIGABYTE GA-P31-S3G Reported by Александр Трубицын - MSI MS-7336 Reported by Benjamin Bellec - MSI X79A-GD45 (8D) (MS-7760)" Reported by mortehu on IRC - Supermicro A1SAi-2550F Reported by Bernard Grymonpon - Supermicro X7DWT Reported by Steven Stremciuc Laptop: - ASUS U38N Reported by Ultra on IRC - Dell Latitude D630 Reported by Márton Miklós - Fujitsu Amilo Xi 3650 Reported by Elmar Stellnberger - Lenovo T400 (whitelisting only) Chipsets: - Mark 8086:1f38 (Intel Avoton/Rangeley) as tested Reported by Jeremy Porter and Bernard Grymonpon - Add Intel Sunrise Point IDs but no support yet. Flash chips: - Atmel AT45DB321D to PREW (+PREW) Reported by The Raven - Eon EN25QH32 to PREW (+PREW) Reported by Josua Mayer - Eon EN25QH64 to PREW (+EW) Reported by David s. Alessio - GigaDevice GD25LQ64(B) to PREW (+PREW) Reported by Greg Tippit - Intel 28F001BN/BX-T to PREW (+EW) Reported by Lu Xie - Micron M25P10-A to PREW (+W) Reported by the Raven - Micron M25PE40 Reported by David Wood - Micron N25Q128..3E to PREW (+PREW) Reported by Miklós Márton - Macronix MX25L3273E to PREW (+PREW) Reported by Roklobsta on IRC - Macronix MX23L6454 to PR (+PR) Reported by Steven Honeyman - Macronix MX25U6435E/F to PREW (+PREW) Reported by Marcos Truchado and Guillermo von Hünefeld - PMC Pm25LQ032C to PREW (+EW) Reported by Dirk Knop - Spansion S25FL016A to PREW (+EW) Reported by Márton Miklós - Spansion S25FL128S......0 to PREW (+PREW) Reported by Jim Houston - Spansion S25FL204K to PR (+PR) Reported by Thomas Debrunner - SST SST49LF016C to PREW (+EW) Reported by Steven Stremciuc - SST SST39VF040 to PREW (+PREW) Reported by Xavier Bourgeois - SST SST49LF040B to PREW (+EW) Reported by Rikard Åhlund - ST M25P10-A to PREW (+W) Reported by Martijn Schiedon - Winbond W39V040FA to PREW (+EW) Reported by Евгений Черкашин - Winbond W39V080FA to PREW (+EW) Reported by protagonist0 on IRC - Winbond W25Q80.W to PREW (+PREW) Reported by Miklós Márton - Winbond W25X64 to PREW (+REW) Reported by Johannes Krampf and Manuel Dejonghe - Fix ID of AMIC A25LQ64 Reported by Roman Titov - Fix page size of Spansion S25FL129P......1 Copy and paste error from the 128S uniform 256kB variant, probably. - Add Micron/Numonyx phase-change memory IDs Miscellaneous: - Detect Android target OS. No changes are required to build flashrom (excluding programmers with NEED_PCI) on Android. - Update rayerspi (spipgm) URL - Fix max_data_write handling of at45db. - Minor refinement of the README - Mark board enable for the GA-K8NS variants as tested. Tested by "nicolae788" on a board with socket 754. - Mark "Multi-system" chassis as non-laptop case. - Remove W836xx log requests. We got enough (and no one is looking at them for the time being anyway). - serprog: improve invalid reply error message, contributed by Urja Rannikko. - Remove default include paths for MinGW. - Disable implicit rules in the Makefile because we don't need them and they just make the build (imperceptibly) slower. - Enable our own strnlen() implementation not only on DJGPP but also if HAVE_STRNLEN is not defined. This is needed to get older BSDs (e.g. NetBSD 6.0, FreeBSD < 8.0) to work. - Tiny other stuff. Corresponding to flashrom svn r1917. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add atapromise programmerJoseph C. Lehner2016-01-161-0/+10
| | | | | | | | | | | | | | | | | | Supported controllers are Promise PDC20262 (FastTrak66/Ultra66), PDC20265 (FastTrak100 Lite/Ultra100), PDC20267 (FastTrak100/Ultra100). At least the Ultra100 only has address lines A0-A14 wired up, limiting addressable chip size to 32 kB. The flash chips mounted on those controllers usually is 128 kB, i.e. parts of the flash chip are inaccessible. As a workaround, the driver implicitly truncates the size of all flash chips to 32 kB. Works well for the factory installed flash. Do NOT use as a generic programmer for chips >32 kB. Corresponding to flashrom svn r1916. Signed-off-by: Joseph C. Lehner <joseph.c.lehner@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Urja Rannikko <urjaman@gmail.com>
* serprog: allow to omit specifying a baud rateStefan Tauner2016-01-041-3/+1
| | | | | | | | | | | On USB-based serial connections (VCP) the requested baud rate usually does not matter (much). Remove the arbitrary restriction and use whatever default values the OS/hardware provides. Corresponding to flashrom svn r1907. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Urja Rannikko <urjaman@gmail.com>
* serprog: Fix FWH/LPC by implementing serprog_mapUrja Rannikko2015-06-291-0/+1
| | | | | | | | | | | | | The serprog protocol does only transmit 24 bit-wide address and ignores the top 8 bit. This is fine as long as the underlying hardware ignores the latter anyway (which is the case for parallel chips that even lack the respective pins). FWH/LPC chips, however, operate on a full 32-bit (LPC) or 28-bit (FWH) address space and would fail with the fallback mapping to NULL. Corresponding to flashrom svn r1895. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add support for the Microchip PICkit2 as an SPI programmerJustin Chevrier2015-02-081-0/+11
| | | | | | | | | | | | | | | This patch was inspired by the code in AVRDude (open source Atmel AVR programmer) to support the PICkit2 written by Doug Brown [1]. The Dediprog code in flashrom was used as the template for this code with some reference to the ft2232 code as well. [1] - https://github.com/steve-m/avrdude/blob/master/pickit2.c Corresponding to flashrom svn r1881. Signed-off-by: Justin Chevrier <jchevrier@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add a bunch of new/tested stuff and various small changes 22Stefan Tauner2015-02-081-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested mainboards: OK: - AOpen UK79G-1394 (used in EZ18 barebones) Reported by Lawrence Gough - ASUS M4N78 SE Reported by Dima Veselov - ASUS P5LD2-VM Mark board enable as tested (reported by Dima Veselov) - GIGABYTE GA-970A-UD3P (rev. 2.0) Reported by trucmar on IRC - GIGABYTE GA-990FXA-UD3 (rev. 4.0) Reported by ROKO__ on IRC - GIGABYTE GA-H77-DS3H (rev. 1.1) Reported by Evgeniy Edigarev - GIGABYTE GA-P55-USB3 (rev. 2.0) Reported by Måns Thörnqvist - MSI MS-7817 (H81M-E33) Reported by Igor Kolker Chipsets: - Marked Intel Bay Trail (0x0f1c) as tested OK Reported by Antonio Ospite - Refine Intel IDs * Add IDs for Braswell * Add IDs for 9 Series PCHs (e.g. H97, Z97) * Rename Wellsburg devices slightly Flash chips: - Atmel AT25DF041A to PREW (+PREW) Reported by Tai-hwa Liang - Atmel AT26DF161 to PREW (+EW) Reported by Steve Shenton - Atmel AT45DB011D to PREW (+PREW) Reported by The Raven - Atmel AT45DB642D to PREW (+PREW) Reported by Mahesh Mokal - Eon EN25F32 to PREW (+PREW) Reported by Arman Khodabande - Eon EN25F40 to PREW (+REW) Reported by Jerrad Pierce - Eon EN25QH16 to PREW (+EW) Reported by Ben Johnson - GigaDevice GD25Q20(B) to PREW (+PREW) Reported by Gilles Aurejac - Macronix MX25U6435E/F to PR (+PR) Reported by Matt Taggart - PMC Pm25LV512(A) to PREW (+PREW) Reported by The Raven - SST SST39VF020 to PREW (+PREW) Reported by Urja Rannikko - Winbond W25Q40.V to PREW (+EW) Reported by Torben Nielsen - Add E variants of MX25Lx006 (MX25L2006E, MX25L4006E, MX25L8006E). - Add MX25L6465E variant. - There was never a MX25L12805 AFAICT. - Split MX25L12805 from models with the same ID but an additional 32 kB eraser: MX25L12835F/MX25L12845E/MX25L12865E. - Add a bunch of ST parallel NOR flash chip IDs. Miscellaneous: - Whitelist ThinkPad X200. - Constify master parameter of register_master(). - Remove FEATURE_BYTEWRITES because it was never used at all. - Refine hwseq messages and make them less prominent. - Fix the yet unused PRIxCHIPADDR format string thingy. - Fix copy&paste error in spi_prettyprint_status_register_bp(). Spotted by Pablo Cases. - Add an additional SMBus controller revision to identify another Yangtze model. Thanks to Dan Christensen for reporting this issue. - dediprog: add missing include for stdlib.h. This fixes (at least) building on FreeBSD and DragonflyBSD with gcc. - Remove references to struct pci_filter from programmer.h. It is only needed in internal.c where it has a complete type. Having it in programmer.h provokes a warning by some old versions of gcc. - Tiny other stuff. Corresponding to flashrom svn r1879. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Unify target OS and CPU architecture checksStefan Tauner2015-01-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | We do CPU architecture checks once for the makefile in arch.h and once for HW access abstraction in hwaccess.c. This patch unifies related files so that they can share the checks to improve maintainability and reduce the chance of inconsistencies. Furthermore, it refines some of the definitions, which - adds "support" for AARCH64 and PPC64, - adds big-endian handling on arm as well as LE handling on PPC64, - fixes compilation of internal.c on AARCH64 and PPC64. Additionally, this patch continues to unify all OS checks in flashrom by adding a new helper macro IS_WINDOWS. The old header file for architecture checking is renamed to platform.h to reflect its broader scope and all new macros are add in there. Corresponding to flashrom svn r1864. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add support for the MSTAR I2C ISP protocolAlexandre Boeglin2014-12-201-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Basically, among other chips, MSTAR manufactures SoCs that equip TV sets and computer screens, and it seems that all of their products use the same in-system programming protocol. Basically, they use the DDC channel of VGA or DVI connectors, which is actually an I2C bus, to encapsulate SPI frames (the flash chip is connected to the SoC through an SPI bus). I wrote this patch since the screen I bought had a software bug, and the manufacturer only released a new firmware binary, but no tool or instructions on flashing it. More details can be found here: http://boeglin.org/blog/index.php?entry=Flashing-a-BenQ-Z-series-for-free(dom) I only read code from Linux kernel archives published by Acer to figure out the protocol (for a touchscreen controller and an NFC chip, both by MSTAR, that share the same ISP protocol), so I don't think there are any legal problems with it. Compilation is currently disabled by default in the Makefile. If in doubt, additional Makefile bugs were added by Stefan. Corresponding to flashrom svn r1860. Signed-off-by: Alexandre Boeglin <alex@boeglin.org> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add support for Intel Wildcat Point PCHDuncan Laurie2014-08-201-0/+1
| | | | | | | | | | | The Wildcat Point PCH can be paired with Broadwell or Haswell. This patch was essentially backported from ChromiumOS commit 9bd2af8. Corresponding to flashrom svn r1845. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add support for Intel Silvermont: Bay Trail, Rangeley and AvotonDuncan Laurie2014-08-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | The core of this patch to support Bay Trail originally came from the Chromiumos flashrom repo and was modified by Sage to support the Rangeley/Avoton parts as well. Because that was not complicated enough already Stefan Tauner refactored and refined everything. Bay Trail seems to be the first Atom SoC able to support hwseq. No SPI Programming Guide could be obtained so it is handled similarly to Lynx Point which seems to be its nearest relative. Corresponding to flashrom svn r1844. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Tested-by: Marc Jones <marcj303@gmail.com> Tested-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Tested-by: Thomas Reardon <thomas_reardon@hotmail.com> Tested-by: Wen Wang <wen.wang@adiengineering.com> Acked-by: Marc Jones <marcj303@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Refine handling chips that exceed maximum programmer sizesStefan Tauner2014-08-151-1/+1
| | | | | | | | | | | | | | | | - Change check_max_decode() to return the number of (common) busses where the flash chip exceeds the supported size of the programmer. - Refine its signature to use a flashctx pointer only. - Move CLI-related bits to cli_classic.c. - Rename check_max_decode() to count_max_decode_exceedings() to better reflect what it (now) really does. - Refine the messages printed by the caller to better integrate with the new setup, and simplify them. Corresponding to flashrom svn r1842. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Refactor some CLI-relevant partsStefan Tauner2014-08-081-1/+0
| | | | | | | | | | | | | | | Begin to move functions that clearly belong to the (command line) user interface out of flashrom's core files like flashrom.c. - Refine messages within check_chip_supported(), rename it to print_chip_support_status() and move it to newly created cli_common.c. - Move flashbuses_to_text() to cli_common.c as well. - Move global verbosity variables to cli_output.c. Corresponding to flashrom svn r1841. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add new programmer for SPI EEPROMs attached to Intel 82580 NICsRicardo Ribalda Delgado2014-07-281-0/+9
| | | | | | | | | | | | | | | | This patch lets you read and write the EEPROM on 82580-based gigabit NIC cards. So far it has been tested on copper NICs only, but other variants employing this controller should work too. It is a nice substitution for the official eeupdate tool. Speed is quite decent: less than 4 seconds for erases or writes of 32 kB. Corresponding to flashrom svn r1832. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Tested-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Rename programmer registration functionsCarl-Daniel Hailfinger2014-07-191-16/+16
| | | | | | | | | | | | Register_programmer suggests that we register a programmer. However, that function registers a master for a given bus type, and a programmer may support multiple masters (e.g. SPI, FWH). Rename a few other functions to be more consistent. Corresponding to flashrom svn r1831. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add selfcheck_board_enables()Stefan Tauner2014-06-121-0/+1
| | | | | | | | | | | | Check for NULL termination of the array, that each board has the two main PCI ID sets defined, that coreboot vendor and model fields are either both set or unset, and that at least either an enable function or a max decode size is available. Corresponding to flashrom svn r1821. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Move global io_base_addr into compilation unitsStefan Tauner2014-06-011-2/+1
| | | | | | | Corresponding to flashrom svn r1813. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add IT8212F as programmerKyösti Mälkki2014-06-011-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | This PCI PATA controller can use 3V parallel flash up to 128 kB. My card was identified as: PCI 1283:8212, subsystem 1283:0001. and labelled as: Innovision Multimedia LTD. EIO ATA133 RAID (DM-8401 Ver A) This particular card did not require setting of any GPIO signals to enable flash writing. My card has Pm39LV512 in PLCC32 package without socket. Rebased by Stefan (automatic cleanup, some PCI changes, changed enable bit handling). Committed with test state NT because the rebased version was not tested on real hardware (yet). Corresponding to flashrom svn r1812. Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add VIA VT6421A LPC programmer driverJonathan Kollasch2014-06-011-0/+10
| | | | | | | | | | | | | | | Due to the mysterious address handling of this chip the user can specify a base address with the offset parameter, e.g.: flashrom -p atavia:offset=0xFFF00000 Thanks to Idwer Vollering for his iterative testing of this code, as well as to Martijn Bastiaan who did the last tests before merging. Corresponding to flashrom svn r1809. Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* sbxxx: Add support for new AMD SPI controllerWei Hu2014-05-161-0/+1
| | | | | | | | | | | | | | This patch adds support for the "SPI 100" SPI engine in Yangtze FCHs (found in Kabini and Temash). Tested reading/writing on ASRock IMB-A180 and PC Engines' APU board. Corresponding to flashrom svn r1794. Signed-off-by: Wei Hu <wei@aristanetworks.com> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add 'const' keyword to chip write and other function prototypesMark Marshall2014-05-091-9/+9
| | | | | | | | | | Corresponding to flashrom svn r1789. Inspired by and mostly based on a patch Signed-off-by: Mark Marshall <mark.marshall@omicron.at> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Make delay values unsignedStefan Tauner2014-05-021-5/+5
| | | | | | | | | | | | | | | There is no reason for negative delays in our use cases: - We don't need it (to work around any quirks). - sleep() (POSIX) uses an unsigned argument. - usleep() (POSIX) uses an unsigned argument. - Sleep() (Windows) uses an unsigned argument. Change all callees as well (without any complications). Corresponding to flashrom svn r1782. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Clean up physmap, fix unaligned mapping problemsCarl-Daniel Hailfinger2014-03-051-1/+2
| | | | | | | | | | | | Convert all physmaps in dmi.c to use aligned readonly maps. Convert all physmaps in cbtable.c to use unaligned readonly maps. Make physunmap() a generic architecture-independent wrapper. Add physunmap_unaligned() to complement physmap*_unaligned(). Corresponding to flashrom svn r1765. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Refactor Intel Chipset EnablesStefan Tauner2013-10-251-6/+6
| | | | | | | | | | | | | | | | | | | | | - Combine enable_flash_ich_4e() and enable_flash_ich_dc() to enable_flash_ich_fwh(). - Remove unjustified (chipset) name parameters from various enable_flash_ich* functions. - Make Poulsbo and Tunnel Creek use generic enables by refining existing functions to work with them, including everything in ichspi.c. - Refactor enable_flash_ich_fwh_decode() to be called unconditionally for all chipsets. - Add support for Intel Atom Centerton (S12x0). - Recombine ICH2/3/4/5 to CHIPSET_ICH2345 because we treat them equally anyway. - Move spibar handling out of ich_init_spi() into enable_flash_ich_spi() - Various small cleanups. Corresponding to flashrom svn r1761. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Use ich_generation parameter in enable functions prior to ICH7Kyösti Mälkki2013-09-141-2/+7
| | | | | | | | | | | Follow the style used from ICH7 onwards to pass ich_generation parameter to lower-level functions on older ICH chipsets too. Corresponding to flashrom svn r1747. Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Remove exit call and mayfail parameter from physmap_common()Niklas Söderlund2013-09-141-1/+1
| | | | | | | | | | | | | | | The only call path where exit was reached was from physmap functions. Callers of physmap() et al. which were not prepared to handle ERROR_PTR return values have been adjusted. physmap_try_ro() has been renamed to physmap_ro() and physmap_common() slightly refactored due to the now removed *FAIL parameters. Corresponding to flashrom svn r1745. Signed-off-by: Niklas Söderlund <niso@kth.se> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add an internal DMI decoderSean Nelson2013-09-111-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously we had to rely on dmidecode to decode the DMI/SMBIOS table. This patch integrates a DMI decoder into flashrom. The old behavior of calling dmidecode can be brought back by using CONFIG_INTERNAL_DMI=no. Significant portions of this patch were taken from dmidecode, hence add its authors to the copyright notice (dmidecode is also GPL2+). We do a few things differently though. First of all we do more bounds checking to prevent accessing unmapped memory. We do not support disovery via EFI (yet), but memory scanning only. We handle the chassis-type lock bit correctly which dmidecode did not for a long while. The API to the rest of flashrom remains stable, but the output changes slightly. To share as much code as possible (which actually is not much), i have added dmi_fill methods that get called in dmi_init. They are reponsible to fill the dmi_strings array and setting the is_laptop variable. After it is called, dmi_init prints all dmi_strings. Previously the strings were printed in the order they were discovered, followed by the chassis-type, which is now output earlier (in dmi_fill). Because DJGPP does not support strnlen a simple implementation was added for it. This is still only available on x86; actually it is not even compiled in for other architectures at all anymore. Corresponding to flashrom svn r1735. Signed-off-by: Sean Nelson <audiohacked@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Tested-by: Maciej Pijanka <maciej.pijanka@gmail.com> Tested-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Get rid of sp_die()Stefan Tauner2013-08-241-1/+0
| | | | | | | | | | | | | | - Add return values to sp_flush_stream(), sp_pass_writen(), sp_execute_opbuf(), sp_execute_opbuf_noflush(), sp_check_opbuf_usage(), sp_do_read_n(). - Use those return values to propagate errors instead of exiting. In some places this has to wait for core API changes (error handling for chip_readb, chip_readn, chip_write) hence comments are added instead. Corresponding to flashrom svn r1719. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Introduce serialport_config()Stefan Tauner2013-08-231-0/+1
| | | | | | | | | | This allows to easily reconfigure a serial port as needed in the Bus Pirate speedup patch. Corresponding to flashrom svn r1717. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Automatically unmap physmap()sStefan Tauner2013-08-141-0/+1
| | | | | | | | | | | | Similarly to the previous PCI self-clean up patch this one allows to get rid of a huge number of programmer shutdown functions and makes introducing bugs harder. It adds a new function rphysmap() that takes care of unmapping at shutdown. Callers are changed where it makes sense. Corresponding to flashrom svn r1714. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add a bunch of new/tested stuff and various small changes 19Stefan Tauner2013-08-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested mainboards: OK: - ASUS P8H77-V LE http://www.flashrom.org/pipermail/flashrom/2013-June/011127.html - HP Pegatron IPMEL-AE (Evans-GL6) Reported by Idwer on IRC - MSI MS-7379 (G31M) http://paste.flashrom.org/view.php?id=1726 - MSI MS-7816 (H87-G43) http://www.flashrom.org/pipermail/flashrom/2013-July/011349.html - MSI MS-9830 (IM-945GSE-A, A9830IMS) http://paste.flashrom.org/view.php?id=1730 - Supermicro X8SAX http://paste.flashrom.org/view.php?id=1717 NOT OK: - Intel D2700MUD http://paste.flashrom.org/view.php?id=1723 - Intel DQ45CB http://www.flashrom.org/pipermail/flashrom/2013-August/011369.html Chipsets: - Add PCI ID for Intel's Coleto Creek. - Mark Intel H87 (0x8c4a) as OK. http://www.flashrom.org/pipermail/flashrom/2013-July/011349.html Miscellaneous: - ichspi: Fix printing address ranges if space is divided by FPB. - Tiny other stuff. Corresponding to flashrom svn r1709. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* sbxxx: Handle active IMCs in AMD chipsetsRudolf Marek2013-07-251-0/+3
| | | | | | | | | | | | Detect and temporarily disable the IMC while accessing the flash. Disable writes on default, but allow the user to enforce it. Corresponding to flashrom svn r1704. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: David Hendricks <dhendrix@google.com>
* Uintptr_t-ify map_flash_region functionsStefan Tauner2013-07-171-5/+5
| | | | | | | | | | | | | | | | | | | Unsigned long is not the right type for manipulating pointer values. Since C99 there are suitable unsigned and signed types available, namely uintptr_t and intptr_t respectively. Use them in functions assigned to programmers' map_flash_region fields and their callers where applicable. This patch also changes the display width of all associated address values in physmap.c to 16/8 hex characters depending on the actual size by introducing a macro PRIxPTR_WIDTH and exploiting printf's * field width specifier. Corresponding to flashrom svn r1701. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Usleep() is not found in all versions of MinGW, use Sleep() on WindowsMaksim Kuleshov2013-04-051-0/+1
| | | | | | | | | | Handle long sleeps on non-Windows correctly. Corresponding to flashrom svn r1667. Signed-off-by: Maksim Kuleshov <mmcx@mail.ru> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Introduce serialport_write_nonblock()Stefan Tauner2013-04-011-0/+1
| | | | | | | | | | | | | It seems useful to have a generic and platform-independent method to read and write to a serial port without blocking. This is the write part. This allows to get rid of the explicit temporary disabling of blocking I/O in serprog's sp_synchronize(). Corresponding to flashrom svn r1662. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Replace sp_sync_read_timeout() with serialport_read_nonblock()Stefan Tauner2013-04-011-0/+1
| | | | | | | | | | | | | | | It seems useful to have a generic and platform-independent method to read and write to a serial port without blocking. This is the read part. It stores the current blocking properties before disabling blocking and restores them after reading. The timeout is implemented as previously by retrying every millisecond until the timeout is reached or enough characters are available. Corresponding to flashrom svn r1661. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add Altera USB-Blaster SPI programmerJames Laird2013-03-271-0/+12
| | | | | | | | | | | | | Adds support for the Altera USB-Blaster programming dongle in Active Serial (AS) mode. Tested on both original product and a clone dongle. Corresponding to flashrom svn r1658. Signed-off-by: James Laird <jhl@mafipulation.org> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add support for Intel Lynx Point low-power and WellsburgDuncan Laurie2013-03-151-1/+3
| | | | | | | | | | | | | | New IDs taken from Intel's patches for the Linux kernel. Also, refine original Lynx Point naming etc. Corresponding to flashrom svn r1656. Based on the chromiumos patch Change-Id: I303a05baa80e4449e70d20adf78ebc7128b88d8e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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