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* Introduce an `include` directory for header filesThomas Heijligen2022-04-291-89/+0
| | | | | | | | | | | | Move all header files to the new `include` directory. Adapt include directives and build systems to the new directory. Change-Id: Iaddd6bbfa0624b166d422f665877f096983bf4cf Signed-off-by: Felix Singer <felix.singer@secunet.com> Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* libflashrom,writeprotect: add flashrom_wp_get_available_ranges()Nikolai Artemiev2022-03-011-0/+9
| | | | | | | | | | | | | | | | Generate list of available ranges by enumerating all possible values that range bits (BPx, TB, ...) can take and using the chip's range decoding function to get the range that is selected by each one. BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom --wp-list Change-Id: Id51f038f03305c8536d80313e52f77d27835f34d Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* libflashrom,writeprotect: add functions for reading/writing WP configsNikolai Artemiev2022-03-011-0/+21
| | | | | | | | | | | | | | | | | | | | | | | New functions are exposed through the libflashrom API for reading/writing chip's WP settins: `flashrom_wp_{read,write}_cfg()`. They read/write an opaque `struct flashrom_wp_cfg` instance, which includes the flash protection range and status register protection mode. This commit also adds `{read,write}_wp_bits()` helper functions that read/write chip-specific WP configuration bits. BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series Change-Id: I3ad25708c3321b8fb0216c3eaf6ffc07616537ad Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* writeprotect.h: add structure to represent chip wp configuration bitsNikolai Artemiev2022-03-011-0/+36
| | | | | | | | | | | | | | | | | | | | | | | Add `struct wp_bits` for representing values of all WP bits in a chip's status/config register(s). It allows most WP code to store and manipulate a chip's configuration without knowing the exact layout of bits in the chip's status registers. Supporting other chips may require additional fields to be added to the structure. BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series Change-Id: I17dee630248ce7b51e624a6e46d7097d5d0de809 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flash.h,flashchips.c: add writeprotect bit layout map to chipsNikolai Artemiev2022-03-011-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds a register bit map `struct reg_bit_info`, with fields for storing the register, bit index, and writability of each bit that affects the chip's write protection. This allows writeprotect code to be independent of the register layout of any specific chip. The new fields have been filled out for example chips. The representation is centered around describing how bits can be accessed and modified, rather than the layout of registers. This is generally easier to work with in code that needs to access specific bits and typically requires specifying the locations of fewer bits overall. BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series Change-Id: Id08d77e6d4ca5109c0d698271146d026dbc21284 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* writeprotect, cli_classic: delete old writeprotect codeNikolai Artemiev2022-02-281-30/+0
| | | | | | | | | | | | | | | | | | | | | Delete writeprotect code that was previously extracted from the cros tree. This is the first of a series of commits adding writeprotect support. Following commits incrementally implement writeprotect operations, culminating in writeprotect support for three example chips: GD25LQ128, GD25Q32, and GD25Q256. BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom -{r,w,E} TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series Change-Id: I67e9b31f86465e5a8f7d3def637198671ee818a8 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* Add writeprotect support infrastructureEdward O'Callaghan2020-09-281-0/+51
The following just lays out the structure for write protect manipulation of SPI flash chips in Flashrom. We later follow up with adding support for each manufacturer group. BUG=b:153800563 BRANCH=none TEST=builds Change-Id: Id93b5a1cb2da476fa8a7dde41d7b963024117474 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40325 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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