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| author | Huaxu Wan <huaxu.wan@linux.intel.com> | 2009-09-23 22:59:43 +0200 |
|---|---|---|
| committer | Jean Delvare <khali@linux-fr.org> | 2009-09-23 22:59:43 +0200 |
| commit | fa08acd7d16cd7ea8114f3844b0ef2505a4276a8 (patch) | |
| tree | 2c02bd54c52c8a7c0354965af194882f8b9252f9 | |
| parent | eccfed42215bebda0acc3158c1a4ff8325dea275 (diff) | |
| download | linux-stable-fa08acd7d16cd7ea8114f3844b0ef2505a4276a8.tar.gz linux-stable-fa08acd7d16cd7ea8114f3844b0ef2505a4276a8.tar.bz2 linux-stable-fa08acd7d16cd7ea8114f3844b0ef2505a4276a8.zip | |
hwmon: (coretemp) Add Lynnfield CPU
Add Lynnfield processor support. Lynnfield is a quad-core Nehalem
based microprocessor for Desktop market, which is introduced in
September 2009.
Signed-off-by: Huaxu Wan <huaxu.wan@linux.intel.com>
Signed-off-by: Kent Liu <kent.liu@linux.intel.com>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
| -rw-r--r-- | Documentation/hwmon/coretemp | 2 | ||||
| -rw-r--r-- | drivers/hwmon/coretemp.c | 6 |
2 files changed, 5 insertions, 3 deletions
diff --git a/Documentation/hwmon/coretemp b/Documentation/hwmon/coretemp index 65d1e667c36e..92267b62db59 100644 --- a/Documentation/hwmon/coretemp +++ b/Documentation/hwmon/coretemp @@ -6,7 +6,7 @@ Supported chips: Prefix: 'coretemp' CPUID: family 0x6, models 0xe (Pentium M DC), 0xf (Core 2 DC 65nm), 0x16 (Core 2 SC 65nm), 0x17 (Penryn 45nm), - 0x1a (Nehalem), 0x1c (Atom). + 0x1a (Nehalem), 0x1c (Atom), 0x1e (Lynnfield) Datasheet: Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A: System Programming Guide http://softwarecommunity.intel.com/Wiki/Mobility/720.htm diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c index c86b1247b94c..caef39cda8c8 100644 --- a/drivers/hwmon/coretemp.c +++ b/drivers/hwmon/coretemp.c @@ -442,11 +442,13 @@ static int __init coretemp_init(void) /* check if family 6, models 0xe (Pentium M DC), 0xf (Core 2 DC 65nm), 0x16 (Core 2 SC 65nm), - 0x17 (Penryn 45nm), 0x1a (Nehalem), 0x1c (Atom) */ + 0x17 (Penryn 45nm), 0x1a (Nehalem), 0x1c (Atom), + 0x1e (Lynnfield) */ if ((c->cpuid_level < 0) || (c->x86 != 0x6) || !((c->x86_model == 0xe) || (c->x86_model == 0xf) || (c->x86_model == 0x16) || (c->x86_model == 0x17) || - (c->x86_model == 0x1A) || (c->x86_model == 0x1c))) { + (c->x86_model == 0x1a) || (c->x86_model == 0x1c) || + (c->x86_model == 0x1e))) { /* supported CPU not found, but report the unknown family 6 CPU */ |