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author | Will Deacon <will.deacon@arm.com> | 2010-07-08 10:58:06 +0100 |
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committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-07-09 11:29:35 +0100 |
commit | 068de8d1be48a04b92fd97f76bb7e113b7be82a8 (patch) | |
tree | a10b8e65776c3d7122799eb7d6b7568d89f1dbbb | |
parent | 4082cfa77680a70e407efdfb207c743107bd8fe4 (diff) | |
download | linux-stable-068de8d1be48a04b92fd97f76bb7e113b7be82a8.tar.gz linux-stable-068de8d1be48a04b92fd97f76bb7e113b7be82a8.tar.bz2 linux-stable-068de8d1be48a04b92fd97f76bb7e113b7be82a8.zip |
ARM: 6211/1: atomic ops: fix register constraints for atomic64_add_unless
The atomic64_add_unless function compares an atomic variable with
a given value and, if they are not equal, adds another given value
to the atomic variable. The function returns zero if the addition
did not occur and non-zero otherwise.
On ARM, the return value is initialised to 1 in C code. Inline assembly
code then performs the atomic64_add_unless operation, setting the
return value to 0 iff the addition does not occur. This means that
when the addition *does* occur, the value of ret must be preserved
across the inline assembly and therefore requires a "+r" constraint
rather than the current one of "=&r".
Thanks to Nicolas Pitre for helping to spot this.
Cc: stable@kernel.org
Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r-- | arch/arm/include/asm/atomic.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h index a0162fa94564..e9e56c00b858 100644 --- a/arch/arm/include/asm/atomic.h +++ b/arch/arm/include/asm/atomic.h @@ -440,7 +440,7 @@ static inline int atomic64_add_unless(atomic64_t *v, u64 a, u64 u) " teq %2, #0\n" " bne 1b\n" "2:" - : "=&r" (val), "=&r" (ret), "=&r" (tmp) + : "=&r" (val), "+r" (ret), "=&r" (tmp) : "r" (&v->counter), "r" (u), "r" (a) : "cc"); |