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author | Catalin Marinas <catalin.marinas@arm.com> | 2012-01-25 11:54:22 +0100 |
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committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-02-02 17:37:42 +0000 |
commit | 6d3ec1ae6cdcda185bd9452b2daed5145e2493a5 (patch) | |
tree | dabf4577ba47d2f7b70741c94353c94f1770b9f8 | |
parent | 91756acb58b17aee68d055fc15b1e2550ff00801 (diff) | |
download | linux-stable-6d3ec1ae6cdcda185bd9452b2daed5145e2493a5.tar.gz linux-stable-6d3ec1ae6cdcda185bd9452b2daed5145e2493a5.tar.bz2 linux-stable-6d3ec1ae6cdcda185bd9452b2daed5145e2493a5.zip |
ARM: 7302/1: Add TLB flushing for both entries in a PMD
Linux uses two PMD entries for a PTE with the classic page table format,
covering 2MB range. However, the __pte_free_tlb() function only adds a
single TLB flush corresponding to 1MB range covering 'addr'. On
Cortex-A15, level 1 entries can be cached by the TLB independently of
the level 2 entries and without additional flushing a PMD entry would be
left pointing at the wrong PTE. The patch limits the TLB flushing range
to two 4KB pages around the 1MB boundary within PMD.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r-- | arch/arm/include/asm/tlb.h | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h index 5d3ed7e38561..314d4664eae7 100644 --- a/arch/arm/include/asm/tlb.h +++ b/arch/arm/include/asm/tlb.h @@ -198,7 +198,15 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte, unsigned long addr) { pgtable_page_dtor(pte); - tlb_add_flush(tlb, addr); + + /* + * With the classic ARM MMU, a pte page has two corresponding pmd + * entries, each covering 1MB. + */ + addr &= PMD_MASK; + tlb_add_flush(tlb, addr + SZ_1M - PAGE_SIZE); + tlb_add_flush(tlb, addr + SZ_1M); + tlb_remove_page(tlb, pte); } |