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| author | Linus Walleij <linus.walleij@linaro.org> | 2017-10-16 16:26:07 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2017-10-19 17:45:22 +0200 |
| commit | 8633e4f2e94a4d12cfb413fedfe4c072a6b99a79 (patch) | |
| tree | f62ef3532bbaf96796a1ffe01fb80c3cbac6a2c9 | |
| parent | be2f9d36b2b39aaf986c2206a64f957c449ac182 (diff) | |
| download | linux-stable-8633e4f2e94a4d12cfb413fedfe4c072a6b99a79.tar.gz linux-stable-8633e4f2e94a4d12cfb413fedfe4c072a6b99a79.tar.bz2 linux-stable-8633e4f2e94a4d12cfb413fedfe4c072a6b99a79.zip | |
ARM: dts: fix PCLK name on Gemini and MOXA ART
These platforms provide a clock to their watchdog, in each
case this is the peripheral clock (PCLK), so explicitly
name the clock in the device tree.
Take this opportunity to add the "faraday,ftwdt010"
compatible as fallback to the watchdog IP blocks.
Cc: Jonas Jensen <jonas.jensen@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| -rw-r--r-- | arch/arm/boot/dts/gemini.dtsi | 3 | ||||
| -rw-r--r-- | arch/arm/boot/dts/moxart.dtsi | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi index c68e8d430234..f0d178c77153 100644 --- a/arch/arm/boot/dts/gemini.dtsi +++ b/arch/arm/boot/dts/gemini.dtsi @@ -145,11 +145,12 @@ }; watchdog@41000000 { - compatible = "cortina,gemini-watchdog"; + compatible = "cortina,gemini-watchdog", "faraday,ftwdt010"; reg = <0x41000000 0x1000>; interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; resets = <&syscon GEMINI_RESET_WDOG>; clocks = <&syscon GEMINI_CLK_APB>; + clock-names = "PCLK"; }; uart0: serial@42000000 { diff --git a/arch/arm/boot/dts/moxart.dtsi b/arch/arm/boot/dts/moxart.dtsi index 1f4c795d3f72..da7b3237bfe9 100644 --- a/arch/arm/boot/dts/moxart.dtsi +++ b/arch/arm/boot/dts/moxart.dtsi @@ -87,9 +87,10 @@ }; watchdog: watchdog@98500000 { - compatible = "moxa,moxart-watchdog"; + compatible = "moxa,moxart-watchdog", "faraday,ftwdt010"; reg = <0x98500000 0x10>; clocks = <&clk_apb>; + clock-names = "PCLK"; }; sdhci: sdhci@98e00000 { |