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| author | Douglas Anderson <dianders@chromium.org> | 2019-04-16 14:53:50 -0700 |
|---|---|---|
| committer | Felipe Balbi <felipe.balbi@linux.intel.com> | 2019-05-03 09:13:48 +0300 |
| commit | d17aa2d262e8574a8c6befb5b6470d1c32875cf8 (patch) | |
| tree | 88083822cd369ea255ab6cac0e72b831ef495a18 | |
| parent | c40cf7705e13d288d900e044c0a2f756e9e4909a (diff) | |
| download | linux-stable-d17aa2d262e8574a8c6befb5b6470d1c32875cf8.tar.gz linux-stable-d17aa2d262e8574a8c6befb5b6470d1c32875cf8.tar.bz2 linux-stable-d17aa2d262e8574a8c6befb5b6470d1c32875cf8.zip | |
ARM: dts: rockchip: Hook resets up to USB PHYs on rk3288.
Let's hook up the resets to the three USB PHYs on rk3288 as per the
bindings. This is in preparation for a future patch that will set the
"snps,reset-phy-on-wake" on the host port.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| -rw-r--r-- | arch/arm/boot/dts/rk3288.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index a024d1e7e74c..3f361fad4684 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -904,6 +904,8 @@ clocks = <&cru SCLK_OTGPHY0>; clock-names = "phyclk"; #clock-cells = <0>; + resets = <&cru SRST_USBOTG_PHY>; + reset-names = "phy-reset"; }; usbphy1: usb-phy@334 { @@ -912,6 +914,8 @@ clocks = <&cru SCLK_OTGPHY1>; clock-names = "phyclk"; #clock-cells = <0>; + resets = <&cru SRST_USBHOST0_PHY>; + reset-names = "phy-reset"; }; usbphy2: usb-phy@348 { @@ -920,6 +924,8 @@ clocks = <&cru SCLK_OTGPHY2>; clock-names = "phyclk"; #clock-cells = <0>; + resets = <&cru SRST_USBHOST1_PHY>; + reset-names = "phy-reset"; }; }; }; |