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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2015-10-07 22:08:24 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2015-11-09 12:50:24 -0800 |
| commit | 41b849066ae71ab5f8d36743814a42ed6be718ae (patch) | |
| tree | 584517f31c55d9a1dc93cbe0d664b0f862adad48 | |
| parent | 6d5138ba774d5a394809a0dccd9f0e06570642cf (diff) | |
| download | linux-stable-41b849066ae71ab5f8d36743814a42ed6be718ae.tar.gz linux-stable-41b849066ae71ab5f8d36743814a42ed6be718ae.tar.bz2 linux-stable-41b849066ae71ab5f8d36743814a42ed6be718ae.zip | |
drm/i915: Restore lost DPLL register write on gen2-4
commit 8e7a65aa70bcc1235a44e40ae0da5056525fe081 upstream.
We accidentally lost the initial DPLL register write in
1c4e02746147 drm/i915: Fix DVO 2x clock enable on 830M
The "three times for luck" hack probably saved us from a total
disaster. But anyway, bring the initial write back so that the
code actually makes some sense.
Reported-and-tested-by: Nick Bowler <nbowler@draconx.ca>
References: http://mid.gmane.org/CAN_QmVyMaArxYgEcVVsGvsMo7-6ohZr8HmF5VhkkL4i9KOmrhw@mail.gmail.com
Cc: Nick Bowler <nbowler@draconx.ca>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c51469051e41..958b26dcac8a 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1451,6 +1451,8 @@ static void i9xx_enable_pll(struct intel_crtc *crtc) I915_WRITE(reg, dpll); + I915_WRITE(reg, dpll); + /* Wait for the clocks to stabilize. */ POSTING_READ(reg); udelay(150); |