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authorAlexander Shiyan <shc_work@mail.ru>2013-12-21 11:11:41 +0400
committerShawn Guo <shawn.guo@linaro.org>2014-02-09 21:33:33 +0800
commit836ac7831d52274dcd1d7f76b0e12215bbac8388 (patch)
treed13a6a4a39f7092dfb4ea9d2e6e62b7984039f3c
parent986cc4920412d8a7b5c9dba85601651f6373f45e (diff)
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ARM: dts: imx27-phytec-phycore-rdk: Add pingrp for SDHC
Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts15
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
index e9a996676140..9997f58a4d14 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
@@ -50,6 +50,19 @@
>;
};
+ pinctrl_sdhc2: sdhc2grp {
+ fsl,pins = <
+ MX27_PAD_SD2_CLK__SD2_CLK 0x0
+ MX27_PAD_SD2_CMD__SD2_CMD 0x0
+ MX27_PAD_SD2_D0__SD2_D0 0x0
+ MX27_PAD_SD2_D1__SD2_D1 0x0
+ MX27_PAD_SD2_D2__SD2_D2 0x0
+ MX27_PAD_SD2_D3__SD2_D3 0x0
+ MX27_PAD_SSI3_FS__GPIO3_28 0x0 /* WP */
+ MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX27_PAD_UART1_TXD__UART1_TXD 0x0
@@ -77,6 +90,8 @@
};
&sdhci2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhc2>;
bus-width = <4>;
cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;