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| author | Rafael J. Wysocki <rjw@sisk.pl> | 2009-01-22 23:39:57 +0100 |
|---|---|---|
| committer | Jesse Barnes <jbarnes@virtuousgeek.org> | 2009-01-27 09:47:10 -0800 |
| commit | 476e7faefc43f106a90b5c96166c59b75de19d30 (patch) | |
| tree | 8226bd551e58c4a4b1f4b23118d6cbbb18b4ea59 | |
| parent | 48f67f54a53bb68619a63c3f38cf7f502ed74b1d (diff) | |
| download | linux-stable-476e7faefc43f106a90b5c96166c59b75de19d30.tar.gz linux-stable-476e7faefc43f106a90b5c96166c59b75de19d30.tar.bz2 linux-stable-476e7faefc43f106a90b5c96166c59b75de19d30.zip | |
PCI PM: Do not wait for buses in B2 or B3 during resume
pci_restore_standard_config() adds extra delay for PCI buses in
low power states (B2 or B3), but this is only correct for buses in
B2, because the buses in B3 are reset when they are put back into
B0. Thus we should wait for such buses to settle after the reset,
but it's not a good idea to wait that long (1.1 s) with interrupts
off.
On the other hand, we have never waited for buses in B2 and B3
during resume and it seems reasonable to go back to this well
tested behaviour.
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| -rw-r--r-- | drivers/pci/pci.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index f0aa3d533839..48807556b47a 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1403,19 +1403,19 @@ int pci_restore_standard_config(struct pci_dev *dev) if (error) return error; - if (pci_is_bridge(dev)) { - if (prev_state > PCI_D1) - mdelay(PCI_PM_BUS_WAIT); - } else { - switch(prev_state) { - case PCI_D3cold: - case PCI_D3hot: - mdelay(pci_pm_d3_delay); - break; - case PCI_D2: - udelay(PCI_PM_D2_DELAY); - break; - } + /* + * This assumes that we won't get a bus in B2 or B3 from the BIOS, but + * we've made this assumption forever and it appears to be universally + * satisfied. + */ + switch(prev_state) { + case PCI_D3cold: + case PCI_D3hot: + mdelay(pci_pm_d3_delay); + break; + case PCI_D2: + udelay(PCI_PM_D2_DELAY); + break; } dev->current_state = PCI_D0; |