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| author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2019-10-02 15:25:42 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-10-11 18:18:35 +0200 |
| commit | 2ed8cd8998cd93ac5088b6253f3986ad89aaf36f (patch) | |
| tree | 5005194975f94972fe54d26c7e0d5f99280ad82a | |
| parent | 2890b718f4a8bab2b4e4ef773cecab2b99ddd5d6 (diff) | |
| download | linux-stable-2ed8cd8998cd93ac5088b6253f3986ad89aaf36f.tar.gz linux-stable-2ed8cd8998cd93ac5088b6253f3986ad89aaf36f.tar.bz2 linux-stable-2ed8cd8998cd93ac5088b6253f3986ad89aaf36f.zip | |
drm/omap: fix max fclk divider for omap36xx
commit e2c4ed148cf3ec8669a1d90dc66966028e5fad70 upstream.
The OMAP36xx and AM/DM37x TRMs say that the maximum divider for DSS fclk
(in CM_CLKSEL_DSS) is 32. Experimentation shows that this is not
correct, and using divider of 32 breaks DSS with a flood or underflows
and sync losts. Dividers up to 31 seem to work fine.
There is another patch to the DT files to limit the divider correctly,
but as the DSS driver also needs to know the maximum divider to be able
to iteratively find good rates, we also need to do the fix in the DSS
driver.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Adam Ford <aford173@gmail.com>
Cc: stable@vger.kernel.org
Link: https://patchwork.freedesktop.org/patch/msgid/20191002122542.8449-1-tomi.valkeinen@ti.com
Tested-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| -rw-r--r-- | drivers/gpu/drm/omapdrm/dss/dss.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/omapdrm/dss/dss.c b/drivers/gpu/drm/omapdrm/dss/dss.c index 41ebb37aaa79..844e1142a122 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss.c +++ b/drivers/gpu/drm/omapdrm/dss/dss.c @@ -1100,7 +1100,7 @@ static const struct dss_features omap34xx_dss_feats = { static const struct dss_features omap3630_dss_feats = { .model = DSS_MODEL_OMAP3, - .fck_div_max = 32, + .fck_div_max = 31, .fck_freq_max = 173000000, .dss_fck_multiplier = 1, .parent_clk_name = "dpll4_ck", |