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| author | Marc Zyngier <marc.zyngier@arm.com> | 2018-03-06 21:44:37 +0000 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-03-21 12:05:45 +0100 |
| commit | 3bf14279499c96539d5c0f06b54336c221ac7c63 (patch) | |
| tree | 03ceec1aab57731e31fabce6be851fbec15e9eeb | |
| parent | 8853101329951ec551cd21d4a6f9c5c4b1a797a0 (diff) | |
| download | linux-stable-3bf14279499c96539d5c0f06b54336c221ac7c63.tar.gz linux-stable-3bf14279499c96539d5c0f06b54336c221ac7c63.tar.bz2 linux-stable-3bf14279499c96539d5c0f06b54336c221ac7c63.zip | |
kvm: arm/arm64: vgic-v3: Tighten synchronization for guests using v2 on v3
commit 27e91ad1e746e341ca2312f29bccb9736be7b476 upstream.
On guest exit, and when using GICv2 on GICv3, we use a dsb(st) to
force synchronization between the memory-mapped guest view and
the system-register view that the hypervisor uses.
This is incorrect, as the spec calls out the need for "a DSB whose
required access type is both loads and stores with any Shareability
attribute", while we're only synchronizing stores.
We also lack an isb after the dsb to ensure that the latter has
actually been executed before we start reading stuff from the sysregs.
The fix is pretty easy: turn dsb(st) into dsb(sy), and slap an isb()
just after.
Cc: stable@vger.kernel.org
Fixes: f68d2b1b73cc ("arm64: KVM: Implement vgic-v3 save/restore")
Acked-by: Christoffer Dall <cdall@kernel.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| -rw-r--r-- | virt/kvm/arm/hyp/vgic-v3-sr.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/virt/kvm/arm/hyp/vgic-v3-sr.c b/virt/kvm/arm/hyp/vgic-v3-sr.c index f5c3d6d7019e..b89ce5432214 100644 --- a/virt/kvm/arm/hyp/vgic-v3-sr.c +++ b/virt/kvm/arm/hyp/vgic-v3-sr.c @@ -215,7 +215,8 @@ void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu) * are now visible to the system register interface. */ if (!cpu_if->vgic_sre) { - dsb(st); + dsb(sy); + isb(); cpu_if->vgic_vmcr = read_gicreg(ICH_VMCR_EL2); } |