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| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2018-12-02 22:42:18 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-12-13 08:52:22 +0100 |
| commit | 9122845dc398e1ab3316e18dc10b469c689c85ce (patch) | |
| tree | 6f0a9a6ef0e1f91481c9d29509cd66a7841ab76e | |
| parent | 90ac7278e652660bd7ffd2e23bfa13893237a344 (diff) | |
| download | linux-stable-9122845dc398e1ab3316e18dc10b469c689c85ce.tar.gz linux-stable-9122845dc398e1ab3316e18dc10b469c689c85ce.tar.bz2 linux-stable-9122845dc398e1ab3316e18dc10b469c689c85ce.zip | |
clk: meson: meson8b: fix the offset of vid_pll_dco's N value
[ Upstream commit 376d8c45bd6ac79f02ecf9ca1606dc5d1b271bc0 ]
Unlike the other PLLs on Meson8b the N value "vid_pll_dco" (a better
name would be hdmi_pll_dco or - as the datasheet calls it - HPLL) is
located at HHI_VID_PLL_CNTL[14:10] instead of [13:9].
This results in an incorrect calculation of the rate of this PLL because
the value seen by the kernel is double the actual N (divider) value.
Update the offset of the N value to fix the calculation of the PLL rate.
Fixes: 28b9fcd016126e ("clk: meson8b: Add support for Meson8b clocks")
Reported-by: Jianxin Pan <jianxin.pan@amlogic.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20181202214220.7715-2-martin.blumenstingl@googlemail.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
| -rw-r--r-- | drivers/clk/meson/meson8b.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 9d79ff857d83..e90af556ff90 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -144,7 +144,7 @@ static struct clk_regmap meson8b_vid_pll = { }, .n = { .reg_off = HHI_VID_PLL_CNTL, - .shift = 9, + .shift = 10, .width = 5, }, .od = { |