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| author | Evalds Iodzevics <evalds.iodzevics@gmail.com> | 2020-04-22 11:17:59 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-04-24 07:57:26 +0200 |
| commit | 27d65e5fe378642ef6d56f26393b9c3b6e94fc8c (patch) | |
| tree | 6616a9500247055e95e5c246fdda956f8f19f126 | |
| parent | eb077831ed8afcb4b68c80ca63be930ac7918bef (diff) | |
| download | linux-stable-27d65e5fe378642ef6d56f26393b9c3b6e94fc8c.tar.gz linux-stable-27d65e5fe378642ef6d56f26393b9c3b6e94fc8c.tar.bz2 linux-stable-27d65e5fe378642ef6d56f26393b9c3b6e94fc8c.zip | |
x86/microcode/intel: replace sync_core() with native_cpuid_reg(eax)
On Intel it is required to do CPUID(1) before reading the microcode
revision MSR. Current code in 4.4 an 4.9 relies on sync_core() to call
CPUID, unfortunately on 32 bit machines code inside sync_core() always
jumps past CPUID instruction as it depends on data structure boot_cpu_data
witch are not populated correctly so early in boot sequence.
It depends on:
commit 5dedade6dfa2 ("x86/CPU: Add native CPUID variants returning a single
datum")
This patch is for 4.4 but also should apply to 4.9
Signed-off-by: Evalds Iodzevics <evalds.iodzevics@gmail.com>
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| -rw-r--r-- | arch/x86/include/asm/microcode_intel.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/include/asm/microcode_intel.h b/arch/x86/include/asm/microcode_intel.h index 90343ba50485..92ce9c8a508b 100644 --- a/arch/x86/include/asm/microcode_intel.h +++ b/arch/x86/include/asm/microcode_intel.h @@ -60,7 +60,7 @@ static inline u32 intel_get_microcode_revision(void) native_wrmsrl(MSR_IA32_UCODE_REV, 0); /* As documented in the SDM: Do a CPUID 1 here */ - sync_core(); + native_cpuid_eax(1); /* get the current revision from MSR 0x8B */ native_rdmsr(MSR_IA32_UCODE_REV, dummy, rev); |