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authorWill Deacon <will.deacon@arm.com>2018-09-18 09:39:55 +0100
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2021-03-07 11:25:56 +0100
commit1b62277f4c057daff9bb44a28b6f781b6dc6e3f2 (patch)
tree7813793280c1d6ef3e906ef7d1a9c4ecc2d20189
parent73dc3ba7d9e9ef7d5e2c0ef7ba80442dc009d468 (diff)
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arm64: cmpxchg: Use "K" instead of "L" for ll/sc immediate constraint
commit 4230509978f2921182da4e9197964dccdbe463c3 upstream. The "L" AArch64 machine constraint, which we use for the "old" value in an LL/SC cmpxchg(), generates an immediate that is suitable for a 64-bit logical instruction. However, for cmpxchg() operations on types smaller than 64 bits, this constraint can result in an invalid instruction which is correctly rejected by GAS, such as EOR W1, W1, #0xffffffff. Whilst we could special-case the constraint based on the cmpxchg size, it's far easier to change the constraint to "K" and put up with using a register for large 64-bit immediates. For out-of-line LL/SC atomics, this is all moot anyway. Reported-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Ben Hutchings <ben@decadent.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--arch/arm64/include/asm/atomic_ll_sc.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/include/asm/atomic_ll_sc.h b/arch/arm64/include/asm/atomic_ll_sc.h
index f02d3bf7b9e6..fb841553b0b0 100644
--- a/arch/arm64/include/asm/atomic_ll_sc.h
+++ b/arch/arm64/include/asm/atomic_ll_sc.h
@@ -268,7 +268,7 @@ __LL_SC_PREFIX(__cmpxchg_case_##name##sz(volatile void *ptr, \
"2:" \
: [tmp] "=&r" (tmp), [oldval] "=&r" (oldval), \
[v] "+Q" (*(u##sz *)ptr) \
- : [old] "Lr" (old), [new] "r" (new) \
+ : [old] "Kr" (old), [new] "r" (new) \
: cl); \
\
return oldval; \