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author | Magnus Damm <damm@opensource.se> | 2011-12-08 22:59:22 +0900 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2011-12-09 18:04:14 +0900 |
commit | 2dacb97d9269e303ed761937a0e9db8711515e08 (patch) | |
tree | 1a26c9587b2008d4bd146ef32bdf36e42a0d6772 | |
parent | 0e027376f896e5dda293ffc8e6e7332d26d2ffc4 (diff) | |
download | linux-stable-2dacb97d9269e303ed761937a0e9db8711515e08.tar.gz linux-stable-2dacb97d9269e303ed761937a0e9db8711515e08.tar.bz2 linux-stable-2dacb97d9269e303ed761937a0e9db8711515e08.zip |
sh: use ioread32/iowrite32 and mapped_reg for div6
Convert the CPG DIV6 helper code to use the new mapped_reg
together with ioread32() and iowrite32().
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
-rw-r--r-- | drivers/sh/clk/cpg.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c index e4a2edf139f7..a0d8faa40baa 100644 --- a/drivers/sh/clk/cpg.c +++ b/drivers/sh/clk/cpg.c @@ -72,7 +72,7 @@ static unsigned long sh_clk_div6_recalc(struct clk *clk) clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, table, NULL); - idx = __raw_readl(clk->enable_reg) & 0x003f; + idx = ioread32(clk->mapped_reg) & 0x003f; return clk->freq_table[idx].frequency; } @@ -98,10 +98,10 @@ static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent) if (ret < 0) return ret; - value = __raw_readl(clk->enable_reg) & + value = ioread32(clk->mapped_reg) & ~(((1 << clk->src_width) - 1) << clk->src_shift); - __raw_writel(value | (i << clk->src_shift), clk->enable_reg); + iowrite32(value | (i << clk->src_shift), clk->mapped_reg); /* Rebuild the frequency table */ clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, @@ -119,10 +119,10 @@ static int sh_clk_div6_set_rate(struct clk *clk, unsigned long rate) if (idx < 0) return idx; - value = __raw_readl(clk->enable_reg); + value = ioread32(clk->mapped_reg); value &= ~0x3f; value |= idx; - __raw_writel(value, clk->enable_reg); + iowrite32(value, clk->mapped_reg); return 0; } @@ -133,9 +133,9 @@ static int sh_clk_div6_enable(struct clk *clk) ret = sh_clk_div6_set_rate(clk, clk->rate); if (ret == 0) { - value = __raw_readl(clk->enable_reg); + value = ioread32(clk->mapped_reg); value &= ~0x100; /* clear stop bit to enable clock */ - __raw_writel(value, clk->enable_reg); + iowrite32(value, clk->mapped_reg); } return ret; } @@ -144,10 +144,10 @@ static void sh_clk_div6_disable(struct clk *clk) { unsigned long value; - value = __raw_readl(clk->enable_reg); + value = ioread32(clk->mapped_reg); value |= 0x100; /* stop clock */ value |= 0x3f; /* VDIV bits must be non-zero, overwrite divider */ - __raw_writel(value, clk->enable_reg); + iowrite32(value, clk->mapped_reg); } static struct clk_ops sh_clk_div6_clk_ops = { @@ -182,7 +182,7 @@ static int __init sh_clk_init_parent(struct clk *clk) return -EINVAL; } - val = (__raw_readl(clk->enable_reg) >> clk->src_shift); + val = (ioread32(clk->mapped_reg) >> clk->src_shift); val &= (1 << clk->src_width) - 1; if (val >= clk->parent_num) { |