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| author | Jisheng Zhang <jszhang@kernel.org> | 2022-02-11 00:49:43 +0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2022-03-16 14:26:49 +0100 |
| commit | f10316c1e99f5f214dc62e5313aae4f680d05fa4 (patch) | |
| tree | 333d48f2d241cc96761abc62d144f0993f45c6e7 | |
| parent | c049b0b7d4022aa273c336f0d4d5ce0c77c57da4 (diff) | |
| download | linux-stable-f10316c1e99f5f214dc62e5313aae4f680d05fa4.tar.gz linux-stable-f10316c1e99f5f214dc62e5313aae4f680d05fa4.tar.bz2 linux-stable-f10316c1e99f5f214dc62e5313aae4f680d05fa4.zip | |
riscv: alternative only works on !XIP_KERNEL
commit c80ee64a8020ef1a6a92109798080786829b8994 upstream.
The alternative mechanism needs runtime code patching, it can't work
on XIP_KERNEL. And the errata workarounds are implemented via the
alternative mechanism. So add !XIP_KERNEL dependency for alternative
and erratas.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Fixes: 44c922572952 ("RISC-V: enable XIP")
Cc: stable@vger.kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| -rw-r--r-- | arch/riscv/Kconfig.erratas | 1 | ||||
| -rw-r--r-- | arch/riscv/Kconfig.socs | 4 |
2 files changed, 3 insertions, 2 deletions
diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas index b44d6ecdb46e..0aacd7052585 100644 --- a/arch/riscv/Kconfig.erratas +++ b/arch/riscv/Kconfig.erratas @@ -2,6 +2,7 @@ menu "CPU errata selection" config RISCV_ERRATA_ALTERNATIVE bool "RISC-V alternative scheme" + depends on !XIP_KERNEL default y help This Kconfig allows the kernel to automatically patch the diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 30676ebb16eb..46a534f04793 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -14,8 +14,8 @@ config SOC_SIFIVE select CLK_SIFIVE select CLK_SIFIVE_PRCI select SIFIVE_PLIC - select RISCV_ERRATA_ALTERNATIVE - select ERRATA_SIFIVE + select RISCV_ERRATA_ALTERNATIVE if !XIP_KERNEL + select ERRATA_SIFIVE if !XIP_KERNEL help This enables support for SiFive SoC platform hardware. |