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| author | Dinh Nguyen <dinguyen@kernel.org> | 2022-01-06 17:53:31 -0600 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2022-03-19 13:48:42 +0100 |
| commit | 71239c2585f4f64fcc0851c57ab5454ffcee6f58 (patch) | |
| tree | 782a0764e6910381ed12f0d4dc52072738979fd7 | |
| parent | 921b65963bf1ca2b8a337dc6b4b09af354670f2e (diff) | |
| download | linux-stable-71239c2585f4f64fcc0851c57ab5454ffcee6f58.tar.gz linux-stable-71239c2585f4f64fcc0851c57ab5454ffcee6f58.tar.bz2 linux-stable-71239c2585f4f64fcc0851c57ab5454ffcee6f58.zip | |
arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg"
[ Upstream commit 268a491aebc25e6dc7c618903b09ac3a2e8af530 ]
The DWC2 USB controller on the Agilex platform does not support clock
gating, so use the chip specific "intel,socfpga-agilex-hsotg"
compatible.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 0dd2d2ee765a..f4270cf18996 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -502,7 +502,7 @@ }; usb0: usb@ffb00000 { - compatible = "snps,dwc2"; + compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; reg = <0xffb00000 0x40000>; interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; phys = <&usbphy0>; @@ -515,7 +515,7 @@ }; usb1: usb@ffb40000 { - compatible = "snps,dwc2"; + compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; reg = <0xffb40000 0x40000>; interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; phys = <&usbphy0>; |