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| author | Krzysztof Kozlowski <krzk@kernel.org> | 2020-06-26 10:06:31 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2023-08-11 11:54:01 +0200 |
| commit | 66579ee141a5fe70f6d87397dc3b57498856f08b (patch) | |
| tree | 6fbc2e18ec37e98544b0be47ab1382ce704384fa | |
| parent | 3b454fb938e114b81fd6717c32dbc84523a820e4 (diff) | |
| download | linux-stable-66579ee141a5fe70f6d87397dc3b57498856f08b.tar.gz linux-stable-66579ee141a5fe70f6d87397dc3b57498856f08b.tar.bz2 linux-stable-66579ee141a5fe70f6d87397dc3b57498856f08b.zip | |
ARM: dts: imx: Align L2 cache-controller nodename with dtschema
[ Upstream commit 69cc1502a87f5ed12e27dbe5fe2bfdd5540826c7 ]
Fix dtschema validator warnings like:
l2-cache@a02000: $nodename:0:
'l2-cache@a02000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Stable-dep-of: ee70b908f77a ("ARM: dts: nxp/imx6sll: fix wrong property name in usbphy node")
Signed-off-by: Sasha Levin <sashal@kernel.org>
| -rw-r--r-- | arch/arm/boot/dts/imx35.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx6sl.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx6sll.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx6sx.dtsi | 2 |
5 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi index 9cbdc1a15cda..d326b18333d1 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/imx35.dtsi @@ -59,7 +59,7 @@ interrupt-parent = <&avic>; ranges; - L2: l2-cache@30000000 { + L2: cache-controller@30000000 { compatible = "arm,l210-cache"; reg = <0x30000000 0x1000>; cache-unified; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index e9955ef12e02..9105e614fe5c 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -255,7 +255,7 @@ interrupt-parent = <&intc>; }; - L2: l2-cache@a02000 { + L2: cache-controller@a02000 { compatible = "arm,pl310-cache"; reg = <0x00a02000 0x1000>; interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 852f66944c7d..452a77552e3d 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -136,7 +136,7 @@ interrupt-parent = <&intc>; }; - L2: l2-cache@a02000 { + L2: cache-controller@a02000 { compatible = "arm,pl310-cache"; reg = <0x00a02000 0x1000>; interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi index cf81c7b949e6..27c253d0fdde 100644 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -137,7 +137,7 @@ interrupt-parent = <&intc>; }; - L2: l2-cache@a02000 { + L2: cache-controller@a02000 { compatible = "arm,pl310-cache"; reg = <0x00a02000 0x1000>; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index b3e24d8bd299..072d5fc9c6db 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -187,7 +187,7 @@ interrupt-parent = <&intc>; }; - L2: l2-cache@a02000 { + L2: cache-controller@a02000 { compatible = "arm,pl310-cache"; reg = <0x00a02000 0x1000>; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |