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| author | Imran Shaik <quic_imrashai@quicinc.com> | 2023-08-03 16:27:38 +0530 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2023-08-13 20:13:17 -0700 |
| commit | 089aad8c769ca0710a66a2adc3e11d94b027b5f7 (patch) | |
| tree | f89381d7b16da7a225e68c556fd236e9b2e60575 | |
| parent | 06d71fa10f2e507444c6759328a6c19d38eab788 (diff) | |
| download | linux-stable-089aad8c769ca0710a66a2adc3e11d94b027b5f7.tar.gz linux-stable-089aad8c769ca0710a66a2adc3e11d94b027b5f7.tar.bz2 linux-stable-089aad8c769ca0710a66a2adc3e11d94b027b5f7.zip | |
clk: qcom: gcc-qdu1000: Add gcc_ddrss_ecpri_gsi_clk support
Add the gcc_ddrss_ecpri_gsi_clk support as per the latest hardware
version of QDU1000 and QRU100 SoCs.
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230803105741.2292309-6-quic_imrashai@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | drivers/clk/qcom/gcc-qdu1000.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index 626c5afed780..991fb2bc97e9 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -1131,6 +1131,26 @@ static struct clk_branch gcc_ddrss_ecpri_dma_clk = { }, }; +static struct clk_branch gcc_ddrss_ecpri_gsi_clk = { + .halt_reg = 0x54298, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x54298, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x54298, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_ddrss_ecpri_gsi_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + static struct clk_branch gcc_ecpri_ahb_clk = { .halt_reg = 0x3a008, .halt_check = BRANCH_HALT_VOTED, @@ -2522,6 +2542,7 @@ static struct clk_regmap *gcc_qdu1000_clocks[] = { [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr, [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, [GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr, + [GCC_DDRSS_ECPRI_GSI_CLK] = &gcc_ddrss_ecpri_gsi_clk.clkr, }; static const struct qcom_reset_map gcc_qdu1000_resets[] = { |