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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-10-03 12:47:59 +0200 |
|---|---|---|
| committer | Rob Herring <robh@kernel.org> | 2023-10-04 08:33:11 -0500 |
| commit | 6df241aacef5f9175b818a80c2ee018697efabc0 (patch) | |
| tree | ad68f816b1a01c496f9a9efad148873046b6d28b | |
| parent | 5d007ffdf6025fe83e497c44ed7c8aa8f150c4d1 (diff) | |
| download | linux-stable-6df241aacef5f9175b818a80c2ee018697efabc0.tar.gz linux-stable-6df241aacef5f9175b818a80c2ee018697efabc0.tar.bz2 linux-stable-6df241aacef5f9175b818a80c2ee018697efabc0.zip | |
dt-bindings: cache: andestech,ax45mp-cache: Fix unit address in example
The unit address in the example does not match the reg property.
Correct the unit address to match reality.
Fixes: 3e7bf4685e42786d ("dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/7b93655219a6ad696dd3faa9f36fde6b094694a9.1696330005.git.geert+renesas@glider.be
Signed-off-by: Rob Herring <robh@kernel.org>
| -rw-r--r-- | Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml index 9ab5f0c435d4..d2cbe49f4e15 100644 --- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml @@ -69,7 +69,7 @@ examples: - | #include <dt-bindings/interrupt-controller/irq.h> - cache-controller@2010000 { + cache-controller@13400000 { compatible = "andestech,ax45mp-cache", "cache"; reg = <0x13400000 0x100000>; interrupts = <508 IRQ_TYPE_LEVEL_HIGH>; |