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| author | Mauro Carvalho Chehab <mchehab+samsung@kernel.org> | 2018-05-07 06:35:41 -0300 |
|---|---|---|
| committer | Jonathan Corbet <corbet@lwn.net> | 2018-05-08 10:02:34 -0600 |
| commit | de0f51e4b1391145e47d6aa60681dab091bcc777 (patch) | |
| tree | 03307fd645fcf3b2c9d45d8cb3711b4143891904 | |
| parent | fe8703cc0de67695e3385ba78b5dfb1091769d50 (diff) | |
| download | linux-stable-de0f51e4b1391145e47d6aa60681dab091bcc777.tar.gz linux-stable-de0f51e4b1391145e47d6aa60681dab091bcc777.tar.bz2 linux-stable-de0f51e4b1391145e47d6aa60681dab091bcc777.zip | |
docs: core-api: add cachetlb documentation
The cachetlb.txt is already in ReST format. So, move it to the
core-api guide, where it belongs.
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
| -rw-r--r-- | Documentation/00-INDEX | 2 | ||||
| -rw-r--r-- | Documentation/core-api/cachetlb.rst (renamed from Documentation/cachetlb.txt) | 0 | ||||
| -rw-r--r-- | Documentation/core-api/index.rst | 1 | ||||
| -rw-r--r-- | Documentation/memory-barriers.txt | 2 | ||||
| -rw-r--r-- | Documentation/translations/ko_KR/memory-barriers.txt | 2 |
5 files changed, 3 insertions, 4 deletions
diff --git a/Documentation/00-INDEX b/Documentation/00-INDEX index 53699c79ee54..04074059bcdc 100644 --- a/Documentation/00-INDEX +++ b/Documentation/00-INDEX @@ -76,8 +76,6 @@ bus-devices/ - directory with info on TI GPMC (General Purpose Memory Controller) bus-virt-phys-mapping.txt - how to access I/O mapped memory from within device drivers. -cachetlb.txt - - describes the cache/TLB flushing interfaces Linux uses. cdrom/ - directory with information on the CD-ROM drivers that Linux has. cgroup-v1/ diff --git a/Documentation/cachetlb.txt b/Documentation/core-api/cachetlb.rst index 6eb9d3f090cd..6eb9d3f090cd 100644 --- a/Documentation/cachetlb.txt +++ b/Documentation/core-api/cachetlb.rst diff --git a/Documentation/core-api/index.rst b/Documentation/core-api/index.rst index c670a8031786..d4d71ee564ae 100644 --- a/Documentation/core-api/index.rst +++ b/Documentation/core-api/index.rst @@ -14,6 +14,7 @@ Core utilities kernel-api assoc_array atomic_ops + cachetlb refcount-vs-atomic cpu_hotplug idr diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index 6dafc8085acc..983249906fc6 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt @@ -2903,7 +2903,7 @@ is discarded from the CPU's cache and reloaded. To deal with this, the appropriate part of the kernel must invalidate the overlapping bits of the cache on each CPU. -See Documentation/cachetlb.txt for more information on cache management. +See Documentation/core-api/cachetlb.rst for more information on cache management. CACHE COHERENCY VS MMIO diff --git a/Documentation/translations/ko_KR/memory-barriers.txt b/Documentation/translations/ko_KR/memory-barriers.txt index 0a0930ab4156..081937577c1a 100644 --- a/Documentation/translations/ko_KR/memory-barriers.txt +++ b/Documentation/translations/ko_KR/memory-barriers.txt @@ -2846,7 +2846,7 @@ CPU 의 캐시에서 RAM 으로 쓰여지는 더티 캐시 라인에 의해 덮 문제를 해결하기 위해선, 커널의 적절한 부분에서 각 CPU 의 캐시 안의 문제가 되는 비트들을 무효화 시켜야 합니다. -캐시 관리에 대한 더 많은 정보를 위해선 Documentation/cachetlb.txt 를 +캐시 관리에 대한 더 많은 정보를 위해선 Documentation/core-api/cachetlb.rst 를 참고하세요. |