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| author | Suzuki K Poulose <suzuki.poulose@arm.com> | 2019-10-24 14:47:50 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-10-29 09:17:09 +0100 |
| commit | eb952c6bce53b5389c41ffc3698594cb43b5aeb9 (patch) | |
| tree | 34b0865436f2d108968a795c898302c86efd9b26 /Documentation/arm64 | |
| parent | 1caa4f72dfc4a0401ec7fad210cfb0ed73d06b4d (diff) | |
| download | linux-stable-eb952c6bce53b5389c41ffc3698594cb43b5aeb9.tar.gz linux-stable-eb952c6bce53b5389c41ffc3698594cb43b5aeb9.tar.bz2 linux-stable-eb952c6bce53b5389c41ffc3698594cb43b5aeb9.zip | |
arm64: Documentation: cpu-feature-registers: Remove RES0 fields
[ Upstream commit 847ecd3fa311cde0f10a1b66c572abb136742b1d ]
Remove the invisible RES0 field entries from the table, listing
fields in CPU ID feature registers, as :
1) We are only interested in the user visible fields.
2) The field description may not be up-to-date, as the
field could be assigned a new meaning.
3) We already explain the rules of the fields which are not
visible.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Dave Martin <dave.martin@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
[ardb: fix up for missing SVE in context]
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'Documentation/arm64')
| -rw-r--r-- | Documentation/arm64/cpu-feature-registers.txt | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/Documentation/arm64/cpu-feature-registers.txt b/Documentation/arm64/cpu-feature-registers.txt index ddd566fea3f2..22cfb86143ee 100644 --- a/Documentation/arm64/cpu-feature-registers.txt +++ b/Documentation/arm64/cpu-feature-registers.txt @@ -110,7 +110,6 @@ infrastructure: x--------------------------------------------------x | Name | bits | visible | |--------------------------------------------------| - | RES0 | [63-52] | n | |--------------------------------------------------| | FHM | [51-48] | y | |--------------------------------------------------| @@ -124,8 +123,6 @@ infrastructure: |--------------------------------------------------| | RDM | [31-28] | y | |--------------------------------------------------| - | RES0 | [27-24] | n | - |--------------------------------------------------| | ATOMICS | [23-20] | y | |--------------------------------------------------| | CRC32 | [19-16] | y | @@ -135,8 +132,6 @@ infrastructure: | SHA1 | [11-8] | y | |--------------------------------------------------| | AES | [7-4] | y | - |--------------------------------------------------| - | RES0 | [3-0] | n | x--------------------------------------------------x @@ -144,7 +139,8 @@ infrastructure: x--------------------------------------------------x | Name | bits | visible | |--------------------------------------------------| - | RES0 | [63-28] | n | + |--------------------------------------------------| + | SVE | [35-32] | y | |--------------------------------------------------| | GIC | [27-24] | n | |--------------------------------------------------| |