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author | Ulrich Hecht <ulrich.hecht+renesas@gmail.com> | 2014-12-10 15:45:22 +0100 |
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committer | Simon Horman <horms+renesas@verge.net.au> | 2014-12-21 17:09:20 +0900 |
commit | ae073881aa7d2f744fa703ae47371611780e4e44 (patch) | |
tree | 946ecfa6535a23f477572383e8c641acf7c68c59 /Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt | |
parent | 97bf6af1f928216fd6c5a66e8a57bfa95a659672 (diff) | |
download | linux-stable-ae073881aa7d2f744fa703ae47371611780e4e44.tar.gz linux-stable-ae073881aa7d2f744fa703ae47371611780e4e44.tar.bz2 linux-stable-ae073881aa7d2f744fa703ae47371611780e4e44.zip |
clk: shmobile: sh73a0 common clock framework implementation
Driver for the SH73A0's clocks that are too specific to be supported by a
generic driver.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt')
-rw-r--r-- | Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt new file mode 100644 index 000000000000..a8978ec94831 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt @@ -0,0 +1,35 @@ +These bindings should be considered EXPERIMENTAL for now. + +* Renesas SH73A0 Clock Pulse Generator (CPG) + +The CPG generates core clocks for the SH73A0 SoC. It includes four PLLs +and several fixed ratio dividers. + +Required Properties: + + - compatible: Must be "renesas,sh73a0-cpg-clocks" + + - reg: Base address and length of the memory resource used by the CPG + + - clocks: Reference to the parent clocks ("extal1" and "extal2") + + - #clock-cells: Must be 1 + + - clock-output-names: The names of the clocks. Supported clocks are "main", + "pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b", + "m1", "m2", "z", "zx", and "hp". + + +Example +------- + + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,sh73a0-cpg-clocks"; + reg = <0 0xe6150000 0 0x10000>; + clocks = <&extal1_clk>, <&extal2_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1", "pll2", + "pll3", "dsi0phy", "dsi1phy", + "zg", "m3", "b", "m1", "m2", + "z", "zx", "hp"; + }; |