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author | Rob Herring <robh@kernel.org> | 2022-08-10 10:16:35 -0600 |
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committer | Lee Jones <lee@kernel.org> | 2022-09-28 16:09:51 +0100 |
commit | 79ea68e0a9cf8c0f479339aca0c60f915522ff32 (patch) | |
tree | 8bb95d18c9f0aa6ab4a85e91d2b96b1732a1aefa /Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml | |
parent | 6460f51ae317aad1d0530e004890e09bff60674d (diff) | |
download | linux-stable-79ea68e0a9cf8c0f479339aca0c60f915522ff32.tar.gz linux-stable-79ea68e0a9cf8c0f479339aca0c60f915522ff32.tar.bz2 linux-stable-79ea68e0a9cf8c0f479339aca0c60f915522ff32.zip |
dt-bindings: mfd: aspeed,ast2x00-scu: Convert to DT schema format
Convert the aspeed,ast2[456]00-scu binding to DT schema format.
The original binding was missing '#address-cells', '#size-cells',
'ranges', and child nodes, so add them.
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20220810161635.73936-3-robh@kernel.org
Diffstat (limited to 'Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml')
-rw-r--r-- | Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml | 110 |
1 files changed, 110 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml new file mode 100644 index 000000000000..1689b986f441 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/aspeed,ast2x00-scu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed System Control Unit + +description: + The Aspeed System Control Unit manages the global behaviour of the SoC, + configuring elements such as clocks, pinmux, and reset. + +maintainers: + - Joel Stanley <joel@jms.id.au> + - Andrew Jeffery <andrew@aj.id.au> + +properties: + compatible: + items: + - enum: + - aspeed,ast2400-scu + - aspeed,ast2500-scu + - aspeed,ast2600-scu + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + ranges: true + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +patternProperties: + '^p2a-control@[0-9a-f]+$': + description: See Documentation/devicetree/bindings/misc/aspeed-p2a-ctrl.txt + type: object + + '^pinctrl(@[0-9a-f]+)?$': + oneOf: + - $ref: /schemas/pinctrl/aspeed,ast2400-pinctrl.yaml + - $ref: /schemas/pinctrl/aspeed,ast2500-pinctrl.yaml + - $ref: /schemas/pinctrl/aspeed,ast2600-pinctrl.yaml + + '^interrupt-controller@[0-9a-f]+$': + description: See Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt + type: object + + '^silicon-id@[0-9a-f]+$': + description: Unique hardware silicon identifiers within the SoC + type: object + additionalProperties: false + + properties: + compatible: + items: + - enum: + - aspeed,ast2400-silicon-id + - aspeed,ast2500-silicon-id + - aspeed,ast2600-silicon-id + - const: aspeed,silicon-id + + reg: + description: + The reg should be the unique silicon id register, and not backwards + compatible one in eg. the 2600. + minItems: 1 + items: + - description: silicon id information registers + - description: unique chip id registers + +required: + - compatible + - reg + - ranges + - '#address-cells' + - '#size-cells' + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + syscon@1e6e2000 { + compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd"; + reg = <0x1e6e2000 0x1a8>; + #clock-cells = <1>; + #reset-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e6e2000 0x1000>; + + silicon-id@7c { + compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id"; + reg = <0x7c 0x4>, <0x150 0x8>; + }; + }; +... |