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authorStephen Boyd <sboyd@codeaurora.org>2017-01-26 15:52:55 -0800
committerStephen Boyd <sboyd@codeaurora.org>2017-01-26 15:52:55 -0800
commit0875dd5938eebe105bdf7357cccca83f310d1b32 (patch)
tree97fb3e86f3855ff22ddc9ecdb605c0bf3311dd3c /Documentation/devicetree
parentf080a493860094a79c613bf64b7d6e0444896e3f (diff)
parent52af8557bb59b0efd731a6e79170486dd91bf85f (diff)
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Merge branch 'clk-stm32f4' into clk-next
* clk-stm32f4: clk: stm32f7: Add stm32f7 clock DT bindings for STM32F746 boards
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/clock/st,stm32-rcc.txt20
1 files changed, 20 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
index 8f19d87cbf24..b240121d2ac9 100644
--- a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
+++ b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
@@ -10,6 +10,7 @@ Required properties:
- compatible: Should be:
"st,stm32f42xx-rcc"
"st,stm32f469-rcc"
+ "st,stm32f746-rcc"
- reg: should be register base and length as documented in the
datasheet
- #reset-cells: 1, see below
@@ -84,6 +85,25 @@ The secondary index is bound with the following magic numbers:
12 CLK_I2SQ_PDIV (post divisor of pll i2s q divisor)
13 CLK_SAIQ_PDIV (post divisor of pll sai q divisor)
+ 14 CLK_HSI (Internal ocscillator clock)
+ 15 CLK_SYSCLK (System Clock)
+ 16 CLK_HDMI_CEC (HDMI-CEC clock)
+ 17 CLK_SPDIF (SPDIF-Rx clock)
+ 18 CLK_USART1 (U(s)arts clocks)
+ 19 CLK_USART2
+ 20 CLK_USART3
+ 21 CLK_UART4
+ 22 CLK_UART5
+ 23 CLK_USART6
+ 24 CLK_UART7
+ 25 CLK_UART8
+ 26 CLK_I2C1 (I2S clocks)
+ 27 CLK_I2C2
+ 28 CLK_I2C3
+ 29 CLK_I2C4
+ 30 CLK_LPTIMER (LPTimer1 clock)
+)
+
Example:
/* Misc clock, FCLK */