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author | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2018-06-29 11:12:47 +0200 |
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committer | Wolfram Sang <wsa@the-dreams.de> | 2018-07-03 23:09:36 +0200 |
commit | bbe899700a44af8b81dcef49f4005d9d1afe7c47 (patch) | |
tree | d9897ddec44388b3194c2a411221a1cf392a9f11 /Documentation/i2c | |
parent | 16d55daa56cd7520055758f98f96e8544cc7713e (diff) | |
download | linux-stable-bbe899700a44af8b81dcef49f4005d9d1afe7c47.tar.gz linux-stable-bbe899700a44af8b81dcef49f4005d9d1afe7c47.tar.bz2 linux-stable-bbe899700a44af8b81dcef49f4005d9d1afe7c47.zip |
i2c: gpio: fault-injector: add incomplete_write_byte
Add another injector for an incomplete transfer. As mentioned in the
docs, this one is important to check bus recovery algorithms with it.
Otherwise random data may be sent to devices!
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Diffstat (limited to 'Documentation/i2c')
-rw-r--r-- | Documentation/i2c/gpio-fault-injection | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/Documentation/i2c/gpio-fault-injection b/Documentation/i2c/gpio-fault-injection index 37542461cea4..a4ce62090fd5 100644 --- a/Documentation/i2c/gpio-fault-injection +++ b/Documentation/i2c/gpio-fault-injection @@ -60,3 +60,22 @@ above, the bus master under test should detect this condition and try a bus recovery. This time, however, it should succeed and the device should release SDA after toggling SCL. +"incomplete_write_byte" +----------------------- + +Similar to above, this file is write only and you need to write the address of +an existing I2C client device to it. + +The injector will again stop at one ACK phase, so the device will keep SDA low +because it acknowledges data. However, there are two differences compared to +'incomplete_address_phase': + +a) the message sent out will be a write message +b) after the address byte, a 0x00 byte will be transferred. Then, stop at ACK. + +This is a highly delicate state, the device is set up to write any data to +register 0x00 (if it has registers) when further clock pulses happen on SCL. +This is why bus recovery (up to 9 clock pulses) must either check SDA or send +additional STOP conditions to ensure the bus has been released. Otherwise +random data will be written to a device! + |