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| author | Michał Mirosław <mirq-linux@rere.qmqm.pl> | 2020-01-15 10:54:35 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-01-29 16:43:19 +0100 |
| commit | 6491a9dd3cf9d92f058d96698d22bf6eb87b9da8 (patch) | |
| tree | 239862797f8afea4215fc3d88c04ce09449925da /Documentation | |
| parent | 3018dc1af52460a4b780dc1e1942470fe1d8ab03 (diff) | |
| download | linux-stable-6491a9dd3cf9d92f058d96698d22bf6eb87b9da8.tar.gz linux-stable-6491a9dd3cf9d92f058d96698d22bf6eb87b9da8.tar.bz2 linux-stable-6491a9dd3cf9d92f058d96698d22bf6eb87b9da8.zip | |
mmc: sdhci: fix minimum clock rate for v3 controller
commit 2a187d03352086e300daa2044051db00044cd171 upstream.
For SDHCIv3+ with programmable clock mode, minimal clock frequency is
still base clock / max(divider). Minimal programmable clock frequency is
always greater than minimal divided clock frequency. Without this patch,
SDHCI uses out-of-spec initial frequency when multiplier is big enough:
mmc1: mmc_rescan_try_freq: trying to init card at 468750 Hz
[for 480 MHz source clock divided by 1024]
The code in sdhci_calc_clk() already chooses a correct SDCLK clock mode.
Fixes: c3ed3877625f ("mmc: sdhci: add support for programmable clock mode")
Cc: <stable@vger.kernel.org> # 4f6aa3264af4: mmc: tegra: Only advertise UHS modes if IO regulator is present
Cc: <stable@vger.kernel.org>
Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/ffb489519a446caffe7a0a05c4b9372bd52397bb.1579082031.git.mirq-linux@rere.qmqm.pl
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'Documentation')
0 files changed, 0 insertions, 0 deletions