diff options
author | Olof Johansson <olof@lixom.net> | 2015-01-12 14:32:47 -0800 |
---|---|---|
committer | Olof Johansson <olof@lixom.net> | 2015-01-12 14:32:47 -0800 |
commit | 58bdda1b571ffeab50874ca851d7473b3d10d03c (patch) | |
tree | 484be483fa78ccb7a77fc145421a5ec05cd02114 /Documentation | |
parent | eaa27f34e91a14cdceed26ed6c6793ec1d186115 (diff) | |
parent | 09bd745b555c262d1e2c851777317f3adf3cf3d4 (diff) | |
download | linux-stable-58bdda1b571ffeab50874ca851d7473b3d10d03c.tar.gz linux-stable-58bdda1b571ffeab50874ca851d7473b3d10d03c.tar.bz2 linux-stable-58bdda1b571ffeab50874ca851d7473b3d10d03c.zip |
Merge tag 'renesas-sh73a0-ccf-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers
Merge "Renesas ARM Based SoC sh73a0 CCF Updates for v3.20" from Simon Horman:
* Add sh73a0 CCF support
* tag 'renesas-sh73a0-ccf-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: sh73a0: disable legacy clock initialization
ARM: shmobile: sh73a0: add MSTP clock assignments to DT
ARM: shmobile: kzm9g-reference: Common clock framework DT description
ARM: shmobile: sh73a0: Common clock framework DT description
ARM: shmobile: sh73a0: Add CPG register bits header
clk: shmobile: sh73a0 common clock framework implementation
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt new file mode 100644 index 000000000000..a8978ec94831 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt @@ -0,0 +1,35 @@ +These bindings should be considered EXPERIMENTAL for now. + +* Renesas SH73A0 Clock Pulse Generator (CPG) + +The CPG generates core clocks for the SH73A0 SoC. It includes four PLLs +and several fixed ratio dividers. + +Required Properties: + + - compatible: Must be "renesas,sh73a0-cpg-clocks" + + - reg: Base address and length of the memory resource used by the CPG + + - clocks: Reference to the parent clocks ("extal1" and "extal2") + + - #clock-cells: Must be 1 + + - clock-output-names: The names of the clocks. Supported clocks are "main", + "pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b", + "m1", "m2", "z", "zx", and "hp". + + +Example +------- + + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,sh73a0-cpg-clocks"; + reg = <0 0xe6150000 0 0x10000>; + clocks = <&extal1_clk>, <&extal2_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1", "pll2", + "pll3", "dsi0phy", "dsi1phy", + "zg", "m3", "b", "m1", "m2", + "z", "zx", "hp"; + }; |