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author | Purna Chandra Mandal <purna.mandal@microchip.com> | 2016-05-17 10:35:55 +0530 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2016-05-28 12:35:03 +0200 |
commit | 684b23c1c189b97d4c5426359029c8fc8d5ecd71 (patch) | |
tree | 8245c9d28aaab3575d66a77c2218650b65a8f6f2 /Documentation | |
parent | 0f2d988d231373bd53d5102bf40792552ed11d87 (diff) | |
download | linux-stable-684b23c1c189b97d4c5426359029c8fc8d5ecd71.tar.gz linux-stable-684b23c1c189b97d4c5426359029c8fc8d5ecd71.tar.bz2 linux-stable-684b23c1c189b97d4c5426359029c8fc8d5ecd71.zip |
dt/bindings: Correct clk binding example for PIC32 SDHCI
Update binding example based on new clock binding documentation.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Joshua Henderson <digitalpeer@digitalpeer.com>
Cc: Andrei Pistirica <andrei.pistirica@microchip.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13265/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt b/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt index 71ad57e050b1..3149297b3933 100644 --- a/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt +++ b/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt @@ -20,7 +20,7 @@ Example: compatible = "microchip,pic32mzda-sdhci"; reg = <0x1f8ec000 0x100>; interrupts = <191 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&REFCLKO4>, <&PBCLK5>; + clocks = <&rootclk REF4CLK>, <&rootclk PB5CLK>; clock-names = "base_clk", "sys_clk"; bus-width = <4>; cap-sd-highspeed; |