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author | Peter Zijlstra <peterz@infradead.org> | 2019-04-24 13:38:23 +0200 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-07-31 07:28:26 +0200 |
commit | 11a6dd0034b6fc3a55ffe1382262797f4aec9f5d (patch) | |
tree | 12b30e5d47098d873421f71b2c62ae203431e1ec /Documentation | |
parent | b1d6b8223ce71ff351d595580b48c9ddd821cda1 (diff) | |
download | linux-stable-11a6dd0034b6fc3a55ffe1382262797f4aec9f5d.tar.gz linux-stable-11a6dd0034b6fc3a55ffe1382262797f4aec9f5d.tar.bz2 linux-stable-11a6dd0034b6fc3a55ffe1382262797f4aec9f5d.zip |
x86/atomic: Fix smp_mb__{before,after}_atomic()
[ Upstream commit 69d927bba39517d0980462efc051875b7f4db185 ]
Recent probing at the Linux Kernel Memory Model uncovered a
'surprise'. Strongly ordered architectures where the atomic RmW
primitive implies full memory ordering and
smp_mb__{before,after}_atomic() are a simple barrier() (such as x86)
fail for:
*x = 1;
atomic_inc(u);
smp_mb__after_atomic();
r0 = *y;
Because, while the atomic_inc() implies memory order, it
(surprisingly) does not provide a compiler barrier. This then allows
the compiler to re-order like so:
atomic_inc(u);
*x = 1;
smp_mb__after_atomic();
r0 = *y;
Which the CPU is then allowed to re-order (under TSO rules) like:
atomic_inc(u);
r0 = *y;
*x = 1;
And this very much was not intended. Therefore strengthen the atomic
RmW ops to include a compiler barrier.
NOTE: atomic_{or,and,xor} and the bitops already had the compiler
barrier.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/atomic_t.txt | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/Documentation/atomic_t.txt b/Documentation/atomic_t.txt index 913396ac5824..ed0d814df7e0 100644 --- a/Documentation/atomic_t.txt +++ b/Documentation/atomic_t.txt @@ -177,6 +177,9 @@ These helper barriers exist because architectures have varying implicit ordering on their SMP atomic primitives. For example our TSO architectures provide full ordered atomics and these barriers are no-ops. +NOTE: when the atomic RmW ops are fully ordered, they should also imply a +compiler barrier. + Thus: atomic_fetch_add(); |