Merge tag 'clk-renesas-for-v4.15-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

Pull Renesas clk driver updates from Geert Uytterhoeven:

  - Add support for the second display unit clock on RZ/G1E,
  - Add git repository to MAINTAINERS,
  - Add suspend/resume support for R-Car Gen3 CPG/MSSR,
  - Small fixes and cleanups.

* tag 'clk-renesas-for-v4.15-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: rcar-gen3: Restore R clock during resume
  clk: renesas: rcar-gen3: Restore SDHI clocks during resume
  clk: renesas: div6: Restore clock state during resume
  clk: renesas: cpg-mssr: Add support to restore core clocks during resume
  clk: renesas: cpg-mssr: Restore module clocks during resume
  MAINTAINERS: Add git repository to Renesas clock driver section
  clk: renesas: cpg-mssr: Add du1 clock to R8A7745
  clk: renesas: rz: clk-rz is meant for RZ/A1
  clk: renesas: r8a77995: Correct parent clock of INTC-AP
  clk: renesas: r8a7796: Correct parent clock of INTC-AP
  clk: renesas: r8a7795: Correct parent clock of INTC-AP

1 files changed, 2 insertions, 2 deletions

diff --git a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
index bb5d942075fb..8ff3e2774ed8 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
@@ -1,6 +1,6 @@
-* Renesas RZ Clock Pulse Generator (CPG)
+* Renesas RZ/A1 Clock Pulse Generator (CPG)
 
-The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable
+The CPG generates core clocks for the RZ/A1 SoCs. It includes the PLL, variable
 CPU and GPU clocks, and several fixed ratio dividers.
 The CPG also provides a Clock Domain for SoC devices, in combination with the
 CPG Module Stop (MSTP) Clocks.