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author | Pawan Gupta <pawan.kumar.gupta@linux.intel.com> | 2019-10-23 12:23:33 +0200 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-11-12 19:21:33 +0100 |
commit | a0808f06dfa1adca8e81716cf773db8c8f1c07b9 (patch) | |
tree | a76516551644140550b6e251179587b1aadb7909 /Documentation | |
parent | 15dfa5d706df85506a527c5572be5ff322031a01 (diff) | |
download | linux-stable-a0808f06dfa1adca8e81716cf773db8c8f1c07b9.tar.gz linux-stable-a0808f06dfa1adca8e81716cf773db8c8f1c07b9.tar.bz2 linux-stable-a0808f06dfa1adca8e81716cf773db8c8f1c07b9.zip |
kvm/x86: Export MDS_NO=0 to guests when TSX is enabled
commit e1d38b63acd843cfdd4222bf19a26700fd5c699e upstream.
Export the IA32_ARCH_CAPABILITIES MSR bit MDS_NO=0 to guests on TSX
Async Abort(TAA) affected hosts that have TSX enabled and updated
microcode. This is required so that the guests don't complain,
"Vulnerable: Clear CPU buffers attempted, no microcode"
when the host has the updated microcode to clear CPU buffers.
Microcode update also adds support for MSR_IA32_TSX_CTRL which is
enumerated by the ARCH_CAP_TSX_CTRL bit in IA32_ARCH_CAPABILITIES MSR.
Guests can't do this check themselves when the ARCH_CAP_TSX_CTRL bit is
not exported to the guests.
In this case export MDS_NO=0 to the guests. When guests have
CPUID.MD_CLEAR=1, they deploy MDS mitigation which also mitigates TAA.
Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Neelima Krishnan <neelima.krishnan@intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Reviewed-by: Josh Poimboeuf <jpoimboe@redhat.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'Documentation')
0 files changed, 0 insertions, 0 deletions