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| author | Paolo Bonzini <pbonzini@redhat.com> | 2019-10-27 09:36:37 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-11-12 19:21:44 +0100 |
| commit | db77548b16521501a287f0e5c8e7754ba35c0193 (patch) | |
| tree | aa0950670ca901af08949fbc264259c403a725d8 /Documentation | |
| parent | 37dfbc8ba7631c3e8fa249056318cad1d7f09f7c (diff) | |
| download | linux-stable-db77548b16521501a287f0e5c8e7754ba35c0193.tar.gz linux-stable-db77548b16521501a287f0e5c8e7754ba35c0193.tar.bz2 linux-stable-db77548b16521501a287f0e5c8e7754ba35c0193.zip | |
KVM: vmx, svm: always run with EFER.NXE=1 when shadow paging is active
commit 9167ab79936206118cc60e47dcb926c3489f3bd5 upstream.
VMX already does so if the host has SMEP, in order to support the combination of
CR0.WP=1 and CR4.SMEP=1. However, it is perfectly safe to always do so, and in
fact VMX also ends up running with EFER.NXE=1 on old processors that lack the
"load EFER" controls, because it may help avoiding a slow MSR write.
SVM does not have similar code, but it should since recent AMD processors do
support SMEP. So this patch makes the code for the two vendors simpler and
more similar, while fixing an issue with CR0.WP=1 and CR4.SMEP=1 on AMD.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Joerg Roedel <jroedel@suse.de>
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'Documentation')
0 files changed, 0 insertions, 0 deletions