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| author | Mischa Jonker <Mischa.Jonker@synopsys.com> | 2019-07-24 14:04:36 +0200 |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2019-08-26 22:35:51 +0530 |
| commit | d85f6b93a76e74f1cbd0c14fb685cc1bc8df9044 (patch) | |
| tree | c0ffc57dd4f9509cf28a41f86dbf375dd9b07e01 /Documentation | |
| parent | 01449985e644329e1fd5c269fff07b9a539eeebf (diff) | |
| download | linux-stable-d85f6b93a76e74f1cbd0c14fb685cc1bc8df9044.tar.gz linux-stable-d85f6b93a76e74f1cbd0c14fb685cc1bc8df9044.tar.bz2 linux-stable-d85f6b93a76e74f1cbd0c14fb685cc1bc8df9044.zip | |
dt-bindings: IDU-intc: Add support for edge-triggered interrupts
This updates the documentation for supporting an optional extra interrupt
cell to specify edge vs level triggered.
Signed-off-by: Mischa Jonker <mischa.jonker@synopsys.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt index c5a1c7b4fc3f..a5c1db95b3ec 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt @@ -8,11 +8,20 @@ Properties: - compatible: "snps,archs-idu-intc" - interrupt-controller: This is an interrupt controller. -- #interrupt-cells: Must be <1>. - - Value of the cell specifies the "common" IRQ from peripheral to IDU. Number N - of the particular interrupt line of IDU corresponds to the line N+24 of the - core interrupt controller. +- #interrupt-cells: Must be <1> or <2>. + + Value of the first cell specifies the "common" IRQ from peripheral to IDU. + Number N of the particular interrupt line of IDU corresponds to the line N+24 + of the core interrupt controller. + + The (optional) second cell specifies any of the following flags: + - bits[3:0] trigger type and level flags + 1 = low-to-high edge triggered + 2 = NOT SUPPORTED (high-to-low edge triggered) + 4 = active high level-sensitive <<< DEFAULT + 8 = NOT SUPPORTED (active low level-sensitive) + When no second cell is specified, the interrupt is assumed to be level + sensitive. The interrupt controller is accessed via the special ARC AUX register interface, hence "reg" property is not specified. |