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author | Bjorn Andersson <andersson@kernel.org> | 2023-04-07 10:27:28 -0700 |
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committer | Bjorn Andersson <andersson@kernel.org> | 2023-04-07 10:27:28 -0700 |
commit | 3a5c7ed3d8ade828ad10dc69094acc56dc58332d (patch) | |
tree | 21f610087b8793dd0aecffbd88cc0740358ce446 /Documentation | |
parent | 93f21d925f787eb4a91e7ade77a544df30be0605 (diff) | |
parent | b065b23d3c3bc91f7e54f9bff4294a7bfbd2afb6 (diff) | |
download | linux-stable-3a5c7ed3d8ade828ad10dc69094acc56dc58332d.tar.gz linux-stable-3a5c7ed3d8ade828ad10dc69094acc56dc58332d.tar.bz2 linux-stable-3a5c7ed3d8ade828ad10dc69094acc56dc58332d.zip |
Merge branch '20230316072940.29137-2-quic_devipriy@quicinc.com' into clk-for-6.4
Merge IPQ9574 Global Clock Controller binding through a topic branch to
allow it also be introduced in the Devicetree source tree.
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml new file mode 100644 index 000000000000..afc68eb9d7cc --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq9574-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on IPQ9574 + +maintainers: + - Anusha Rao <quic_anusha@quicinc.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on IPQ9574 + + See also:: + include/dt-bindings/clock/qcom,ipq9574-gcc.h + include/dt-bindings/reset/qcom,ipq9574-gcc.h + +properties: + compatible: + const: qcom,ipq9574-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: Bias PLL ubi clock source + - description: PCIE30 PHY0 pipe clock source + - description: PCIE30 PHY1 pipe clock source + - description: PCIE30 PHY2 pipe clock source + - description: PCIE30 PHY3 pipe clock source + - description: USB3 PHY pipe clock source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + clock-controller@1800000 { + compatible = "qcom,ipq9574-gcc"; + reg = <0x01800000 0x80000>; + clocks = <&xo_board_clk>, + <&sleep_clk>, + <&bias_pll_ubi_nc_clk>, + <&pcie30_phy0_pipe_clk>, + <&pcie30_phy1_pipe_clk>, + <&pcie30_phy2_pipe_clk>, + <&pcie30_phy3_pipe_clk>, + <&usb3phy_0_cc_pipe_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... |