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author | Linus Torvalds <torvalds@linux-foundation.org> | 2016-05-19 09:46:18 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2016-05-19 09:46:18 -0700 |
commit | 0efacbbaee1e94e9942da0912f5b46ffd45a74bd (patch) | |
tree | a17933437de955f4ce5e74760610bab75f2ae385 /arch/arc/plat-axs10x | |
parent | f4f27d0028aabce57e44c16c2fdefccd6310d2f3 (diff) | |
parent | 776d7f1694a7d678291354a05f0243965708306a (diff) | |
download | linux-stable-0efacbbaee1e94e9942da0912f5b46ffd45a74bd.tar.gz linux-stable-0efacbbaee1e94e9942da0912f5b46ffd45a74bd.tar.bz2 linux-stable-0efacbbaee1e94e9942da0912f5b46ffd45a74bd.zip |
Merge tag 'arc-4.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC updates from Vineet Gupta:
"We have a relatively big changeset for ARC for 4.7.
The highlight is support for EZChip (now Mellanox) NPS-400 network
processor, a 400-Gb throughput C-programmable packet processor based
on ARC700 cores from Synopsys. See
http://www.mellanox.com/related-docs/prod_npu/PB_NPS-400.pdf
Also present are irqchip and clocksource drivers for NPS as agreed
with respective maintainers to go via ARC tree due to an soc header
dependency. I have the needed ACKs from Jason, Marc, Daniel. You
might run into a trivial merge conflict in drivers/irqchip/*
This EZChip platform support required some deep changes in ARC
architecture code and also opportunity to cleanup past sins (legacy
irq domains, missing irq domain lookup, hard coded timer irqs...)
Summary:
- Support for EZChip (now Mellanox) NPS-400 Network processor based
on ARC700
- NPS interrupt controller and clocksource drivers
- ARC timers probed off DT
- ARC iqrchips switching to linear domain (upgrade from legacy
domains)"
* tag 'arc-4.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: (37 commits)
arc: axs103_smp: Fix CPU frequency to 100MHz for dual-core
arc: axs10x: Add DT bindings for I2S PLL Clock
ARC: pae: STRICT_MM_TYPECHECKS was broken
ARC: Add eznps platform to Kconfig and Makefile
ARC: [plat-eznps] Use dedicated COMMAND_LINE_SIZE
ARC: [plat-eznps] Use dedicated cpu_relax()
ARC: [plat-eznps] Use dedicated identity auxiliary register.
ARC: [plat-eznps] Use dedicated SMP barriers
ARC: [plat-eznps] Use dedicated atomic/bitops/cmpxchg
ARC: [plat-eznps] Use dedicated user stack top
ARC: [plat-eznps] Add eznps platform
ARC: [plat-eznps] Add eznps board defconfig and dts
ARC: Mark secondary cpu online only after all HW setup is done
ARC: rwlock: disable interrupts in !LLSC variant
ARC: Make vmalloc size configurable
ARC: clean out UAPI byteorder.h clean off Kconfig symbol
irqchip: add nps Internal and external irqchips
clocksource: Add NPS400 timers driver
soc: Support for EZchip SoC
Documentation: Add EZchip vendor to binding list
...
Diffstat (limited to 'arch/arc/plat-axs10x')
-rw-r--r-- | arch/arc/plat-axs10x/axs10x.c | 27 |
1 files changed, 20 insertions, 7 deletions
diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat-axs10x/axs10x.c index 1b0f0f458a2b..86548701023c 100644 --- a/arch/arc/plat-axs10x/axs10x.c +++ b/arch/arc/plat-axs10x/axs10x.c @@ -14,10 +14,11 @@ * */ +#include <linux/of_fdt.h> #include <linux/of_platform.h> +#include <linux/libfdt.h> #include <asm/asm-offsets.h> -#include <asm/clk.h> #include <asm/io.h> #include <asm/mach_desc.h> #include <asm/mcip.h> @@ -389,6 +390,13 @@ axs103_set_freq(unsigned int id, unsigned int fd, unsigned int od) static void __init axs103_early_init(void) { + int offset = fdt_path_offset(initial_boot_params, "/cpu_card/core_clk"); + const struct fdt_property *prop = fdt_get_property(initial_boot_params, + offset, + "clock-frequency", + NULL); + u32 freq = be32_to_cpu(*(u32*)(prop->data)) / 1000000, orig = freq; + /* * AXS103 configurations for SMP/QUAD configurations share device tree * which defaults to 90 MHz. However recent failures of Quad config @@ -401,12 +409,10 @@ static void __init axs103_early_init(void) #ifdef CONFIG_ARC_MCIP unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F; if (num_cores > 2) - arc_set_core_freq(50 * 1000000); - else if (num_cores == 2) - arc_set_core_freq(75 * 1000000); + freq = 50; #endif - switch (arc_get_core_freq()/1000000) { + switch (freq) { case 33: axs103_set_freq(1, 1, 1); break; @@ -431,11 +437,18 @@ static void __init axs103_early_init(void) * DT "clock-frequency" might not match with board value. * Hence update it to match the board value. */ - arc_set_core_freq(axs103_get_freq() * 1000000); + freq = axs103_get_freq(); break; } - pr_info("Freq is %dMHz\n", axs103_get_freq()); + pr_info("Freq is %dMHz\n", freq); + + /* Patching .dtb in-place with new core clock value */ + if (freq != orig ) { + freq = cpu_to_be32(freq * 1000000); + fdt_setprop_inplace(initial_boot_params, offset, + "clock-frequency", &freq, sizeof(freq)); + } /* Memory maps already config in pre-bootloader */ |