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authorKrzysztof Kozlowski <krzk@kernel.org>2020-06-26 10:06:02 +0200
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2020-07-22 09:33:04 +0200
commit2e224b5d314941509dd0219408d9bd692bf15e64 (patch)
treee7ad9077df5e31948948c67ec4a6990d3daf45fa /arch/arm/boot/dts/wm8650.dtsi
parentc8a4452da9f4b09c28d904f70247b097d4c14932 (diff)
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ARM: dts: socfpga: Align L2 cache-controller nodename with dtschema
[ Upstream commit d7adfe5ffed9faa05f8926223086b101e14f700d ] Fix dtschema validator warnings like: l2-cache@fffff000: $nodename:0: 'l2-cache@fffff000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' Fixes: 475dc86d08de ("arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC") Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/wm8650.dtsi')
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